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A SiGe p-channel FET has been fabricated with LPCVD epitaxy and thin gate oxide at low temperatures. With a Ge content of 20% a Si/SiGe/Si quantum well with 0.15eV depth and 10nm thickness is formed in the valence band. Compared with a bulk Si p-channel transistor peak mobility is increased by about 50%. High mobility, 0.4μm gate length and 5nm gate oxide result in high saturation current of 0.22mA/μm...
The influence of high-concentration phosphorus diffusion on an antimony marker layer separated spatially by 4??m epitaxially deposited silicon is described. The phosphorus was implanted into a deposited polysilicon layer to eliminate the effects of implantation enhanced diffusion and point-defect generation due to phosphorus precipitation on the diffusion of the antimony marker layer. It was found...
This paper reports an investigation of non-ideal base currents in epitaxial base (Si or Si1-xGex) bipolar transistors fabricated using a single-polysilicon self-aligned technology. Two independent leakage components are identified. Their spatial and physical origins are used to outline the main critical fabrication steps of this technology.
In this article several features of the selective epitaxial growth of SiGe by LPCVD are discussed, such as the pad size dependence of growth rate, composition and strain relaxation. Finally, intense photoluminescence from sub??m dots with SiGe/Si multiple quantum wells is presented.
A study is made of fluorine implantation into polysilicon for application in npn polysilicon emitter bipolar transistors. Polysilicon sheet resistance measurements are used to monitor the effect of the fluorine on the epitaxial realignment of the polysilicon, and this is correlated with device electrical results. It is shown that the fluorine causes epitaxial realignment of the polysilicon to occur...
A vertical GaAs FET with sub-??m gate length has been grown using selective epitaxy. The gate structure of this device consists of an insulator/metal/insulator multilayer. The advantage of this structure is the reduction of the gate-source and gate-drain capacitances due to the relatively low dielectric constant of the insulator. In addition the insulator above the metal gate enables to use the selective...
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