A SiGe p-channel FET has been fabricated with LPCVD epitaxy and thin gate oxide at low temperatures. With a Ge content of 20% a Si/SiGe/Si quantum well with 0.15eV depth and 10nm thickness is formed in the valence band. Compared with a bulk Si p-channel transistor peak mobility is increased by about 50%. High mobility, 0.4μm gate length and 5nm gate oxide result in high saturation current of 0.22mA/μm and transconductance of 180mS/mm at 2.5V. 30% increase is due to the SiGe layer. Integration of the SiGe p-FET into CMOS with relatively low process complexity is possible in combination with a Si n-FET.