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A SiGe p-channel FET has been fabricated with LPCVD epitaxy and thin gate oxide at low temperatures. With a Ge content of 20% a Si/SiGe/Si quantum well with 0.15eV depth and 10nm thickness is formed in the valence band. Compared with a bulk Si p-channel transistor peak mobility is increased by about 50%. High mobility, 0.4μm gate length and 5nm gate oxide result in high saturation current of 0.22mA/μm...
Multilevel metallization is a key process for the technology generations below 0.5μm. As the design rules are going smaller, the limits of the classical SOG Etch-Back process are reached in terms of process complexity and long distance planarization. The solution to this problem is to use a Chemical Mechanical Polishing technique for the dielectric planarization. In this paper, we will demonstrate...
This paper describes an approach to the major issues of Design for Manufacturability (DFM) based on Principal Component Analysis and Design of Experiments techniques, which has been formulated and implemented for a 1??m CMOS technology, culminating in the generation of realistic nominal and worst-case model parameter sets.
We have verified the design of latchup-free bulk CMOS devices for operating temperatures up to 525K by simulation and measurement using a 1.0 micrometer twin tub ASIC process with epitaxial layer. It is possible to achieve an increase in holding voltage with rising temperature by applying design precautions. A special ASIC cell library for high temperature circuit operation has been developed and...
Integrated microsensors are miniaturised sensors with on-chip signal conditioning circuitry based on integrated circuit (IC) technologies such as CMOS or bipolar technology. Microsensor modules with one or several sensor elements and on-chip circuitry are essential building blocks of microsystems. Silicon micromachining is the basis of miniaturised mechanical, thermal, and fluid sensors and actuators...
The objectives, composition and organisation of the SUSTAIN network on submicron silicon technology are reviewed. A few highlights of the network's achievements are discussed and some practical information is provided.
In this paper, we present a novel electrostatic discharge (ESD) protection device which is, against the catastrophic ESD attack, activated as either a reverse-biased punchthrough bipolar junction transistor (BJT) or a forward-biased diode, depending on the polarity of the input pulse. Experimental data show that the new device is more efficient and area-effective than any other conventional one. It...
The most recent issues about the low frequency noise in CMOS devices are presented. The various approaches such as the carrier number and the Hooge mobility fluctuations schemes currently used for the interpretation of the noise sources are discussed. The main physical properties which characterize the Random Telegraph Signals in small area MOS transistors are reviewed. The impact of the miniaturization...
This paper investigates the suitability and applicability of heavy ion implants (indium for NMOS and arsenic or antimony for PMOS) for better channel profiling in advanced CMOS technologies. Such important technological issues as post-implantation damage, the risk of room-temperature freeze-out, the danger of out-diffusion during oxidation, implantation and diffusion modelling for process optimisation,...
The feasibility and the limitations of ultra-low-power CMOS technologies are investigated using process and device simulation, followed by post-processing of the simulated IV data. On the basis of simplified modern state-of-the-art processes and special scaling a set of possible ultra-low-power CMOS processes was developed and analyzed for their performance on the gate level.
A novel process technology has been developed for "smart" analog and mixed-signal products requiring embedded EEPROM. The technology is a modular addition to a 0.8 μm, single polysilicon, double metal baseline CMOS process. The EEPROM process architecture is defined with the primary goal of minimizing the number of additional process steps driven by wafer cost considerations. A double polysilicon...
For a 0.35 μm CMOS technology, an optimized poly buffered LOCOS process is necessary in order to meet the design rules. In this paper, the feasibility of this isolation scheme is demonstrated.
A high performance 0.35 μm CMOS technology is presented for low operating voltages. The increased reliability margin at low supply voltages was used to scale the gate oxide thickness and optimize the channel and source/drain junctions profiles. The resulting well controlled short-channel behaviour of the devices was used to obtain low leakage current at low threshold voltages. Good circuit performance...
CMOS SOI devices, realised on very thin silicon film on SIMOX material, are very attractive for ULSI application. There are many advantages over bulk that have been frequently emphasised in the literature [1]. For sub-quarter micron devices, there are several candidate architectures and device operations, depending on the gate material: - enhancement mode Partially or Fully Depleted devices, for a...
The low-frequency (LF) noise behaviour of Silicon-on-Insulator MOSFETs fabricated in different SOI CMOS technologies is reported. It is shown that the kink-related excess LF noise, typical for the floating operation of partially depleted transistors can be eliminated by a proper choice of technology, i.e., either by using a fully depleted technology, or so-called dual-gate (gate-all-around) structures...
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