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In this work a review of the basic concepts of recently developed two-dimensional profiling techniques is given. The methods are based on spreading resistance measurements, atomic force surface topography and transmission electron microscopy. The use of spreading resistance for two-dimensional profiling has been introduced three years ago. In the mean time the experimental procedure and the interpretation...
Biased polysilicon field plates [1] are used to achieve 800-V wiring in a typical junction isolated, high voltage integrated circuit. The field plates are biased by phosphorous doped polysilicon resistors, connected in a voltage division scheme to the high voltage wire. The effect of using doped (as opposed to undoped), polysilicon resistors on field plate potential distribution is investigated. It...
Phenomena related to oxygen precipitation in Czochralski grown silicon subjected to hydrostatic pressure up to 2.5 GPa at ambient temperature and up to 1.35 GPa at 1230 - 1620K were investigated by FTIR, X-ray methods, chemical selective etching and TEM. Depending on the initial oxygen concentration and preannealing conditions, uniform stress influences markedly the oxygen - related defect structure...
Modulation-doped GaAs/In0.25Ga0.75As/Al0.3Ga0.7 As HEMT structures were grown using different MBE-growth temperatures and In0.25Ga0.75As channel thicknesses. Drain current DLTS measurements performed on these samples using a Fourier-Transform technique show that the concentrations of both bulk and interface traps depend greatly on growth temperature. In addition, a broadening of one of the DLTS peaks...
In this paper, a new switching device having a p-type delta-oped sheet, ??(p+), in the center of an InGaAs-GaAs quantum well is presented. An N-shaped negative-differential -resistance (NDR) phenomenon resulting from the resonant tunneling effect through the miniband under a proper anode-to-cathode voltage is observed. From the experimental results, it is seen that the temperature plays an important...
The operation of inverters, fabricated in a 1 ??m partially depleted SOI CMOS technology is investigated from room temperature down to liquid helium. It is demonstrated that the transfer characteristics suffer from the floating-body anomalies, like the kink and the breakdown/latch behaviour. Additionally, at 4.2 K, hysteresis, which is related to the cryogenic (freeze-out) behaviour of the n-MOSFETs...
We show that a remarkable threshold shift ??Vp and an increase in the saturation current ??Ids can be observed in AlGaAs/InGaAs PM-HEMT's submitted to high temperature (100??C - 200 ??C) storage or hot-electron stresses for relatively short times (about 20 hours). An increase in Ids up to 40% has been observed. The increase is not permanent and can be recovered by a room or low temperature storage...
The use of numerical simulation has become an invaluable tool in the competitive environment of technology and device development. Effective process and device simulation can reduce the time and cost associated with new product development and can provide a means for rapid assessment of new design concepts. The scaling of voltages and geometries in flash EEPROM has highlighted the need for models...
The temperature dependence of the Fowler-Nordheim tunnel current in a MOS structure is investigated both theoretically and experimentally between 25?? C and 400??C. The F-N current is found to increase substantially with temperature. The existence of effective pre-exponential and exponential F-N coefficients up to 400??C is demonstrated and validated by numerical simulations based on the general F-N...
The volume degradation features of very thin tunnel oxide layers will be deeply analyzed and the validity of the following issues will be demonstrated quantitatively: i) only negative charge builds-up in the bulk of the insulator layer, ii) for a given oxide thickness and gate stress polarity breakdown occurs as soon as the negative trapped bulk oxide charge density attains a critical value, iii)...
A SiGe p-channel FET has been fabricated with LPCVD epitaxy and thin gate oxide at low temperatures. With a Ge content of 20% a Si/SiGe/Si quantum well with 0.15eV depth and 10nm thickness is formed in the valence band. Compared with a bulk Si p-channel transistor peak mobility is increased by about 50%. High mobility, 0.4μm gate length and 5nm gate oxide result in high saturation current of 0.22mA/μm...
Typical 2D effects such as oxide thinning and bird's beak size decrease with nitride masks and windows size reduction are observed in submicron isolation structures. Such phenomena depend on the stresses generated by the oxidation process and consequently on the mechanical properties of the IC-materials. In this paper, an elastovisco-plastic modelling of the silicon oxidation is used for the calibration...
Removal of photoresist after plasma metal etch becomes more difficult as the metal etch requirement and metallization systems become more complicated. We have found that the most effective method to remove the damaged metal oxide surface caused by oxygen plasma ash is to use a patented (USP 5,279,771) buffered hydroxylamine reducing solution (EKC-265). Auger analysis indicated the complete removal...
Lithography has enabled the continuous shrinking of device geometry over many years. Whereas it has been predicted many times that optical lithography would run out of steam, it still is the technology of choice, and this will certainly remain for a considerable time. In this paper various optical lithography techniques for 0.25 μm feature printing will be reviewed. The issues related to deep-UV lithography...
The influence of high-concentration phosphorus diffusion on an antimony marker layer separated spatially by 4??m epitaxially deposited silicon is described. The phosphorus was implanted into a deposited polysilicon layer to eliminate the effects of implantation enhanced diffusion and point-defect generation due to phosphorus precipitation on the diffusion of the antimony marker layer. It was found...
Multilevel metallization is a key process for the technology generations below 0.5μm. As the design rules are going smaller, the limits of the classical SOG Etch-Back process are reached in terms of process complexity and long distance planarization. The solution to this problem is to use a Chemical Mechanical Polishing technique for the dielectric planarization. In this paper, we will demonstrate...
The European Laboratory for Electronic Noise is a Network in the Human Capital and Mobility EEC program. This network gathers nine institutions, working in the domain of fluctuations and electronic noise. Its main purposes are to promote collaborations and to favour exchanges of researchers between laboratories, and to ensure a co-ordination among institutions working on noise problems. After one...
The aim of this paper is to present the numerical simulation of the influence of the SALICIDE (self-aligned silicide) process on MOSFET (metal oxide semiconductor field effect transistor) technology. First, we report on the geometrical effects which appear during the growth of the titanium silicide (TiSi2) layer over Si-poly gate. Then, silicidation over boron doped source/drain shallow junctions...
The Monte Carlo simulator IMSIL [2] has been extended to take arbitrarily shaped 2-D structures into account. The lateral dose distribution at a mask edge is studied and compared with lateral SIMS measurements. The lateral dose distributions for boron and arsenic in amorphous and crystalline silicon are compared.
This paper describes an approach to the major issues of Design for Manufacturability (DFM) based on Principal Component Analysis and Design of Experiments techniques, which has been formulated and implemented for a 1??m CMOS technology, culminating in the generation of realistic nominal and worst-case model parameter sets.
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