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A SiGe p-channel FET has been fabricated with LPCVD epitaxy and thin gate oxide at low temperatures. With a Ge content of 20% a Si/SiGe/Si quantum well with 0.15eV depth and 10nm thickness is formed in the valence band. Compared with a bulk Si p-channel transistor peak mobility is increased by about 50%. High mobility, 0.4μm gate length and 5nm gate oxide result in high saturation current of 0.22mA/μm...
This paper reports on an efficient methodology to optimise conventional channel and Pulse Shaped Doping profile (PSD). We clarify the different physical phenomena responsible of leakage current increasing, then we compare and discuss the impact of the optimised profiles on device performances in term of current drivability, Drain Induced Barrier Lowering (DIBL), mobility and speed considerations.
In this paper the electrical performance of submicron MOS transistors at low temperatures is explored. This way we found that second-order effects like; the bias dependent series resistance, the second substrate current hump and some others, are amplified allowing so an easier way to study them and to determine their physical origin.
A novel mutual channel (MUCH) device for switching high voltage on a small chip area is presented. The device layout is composed of two interacting MOS-transistors. The two transistors are stacked on each other and separated by a shared gate oxide. By this concept idea, a mutual channel device with beneficial high voltage behaviour and without any ordinary drift region can be designed. Simulation...
Low temperature polysilicon thin film transistors suitable with active-matrix applications are elaborated. Electrical performances can be significantly improved by using a lightly in-situ doped drain. OFF state current can be reduced more than a decade for low drain voltage (Ids ?? 10 pA for Vds ≪ 1 V) in comparison with a heavily in-situ doped drain. Consequently, ON/OFF state current ratio is much...
The feasibility and the limitations of ultra-low-power CMOS technologies are investigated using process and device simulation, followed by post-processing of the simulated IV data. On the basis of simplified modern state-of-the-art processes and special scaling a set of possible ultra-low-power CMOS processes was developed and analyzed for their performance on the gate level.
A novel high gate barrier (HGB) AlInAs/GaInAs/InP HEMT structure is proposed, which overcomes gate leakage current problems due to limited Schottky barrier height in common HEMT design. Gate leakage is a major contribution to low-frequency noise besides deep trap re-charging (1). The crucial point in the novel HEMT design is the insertion of an additional shallow p+-?? doped plane below the gate contact...
For a 0.35 μm CMOS technology, an optimized poly buffered LOCOS process is necessary in order to meet the design rules. In this paper, the feasibility of this isolation scheme is demonstrated.
A high performance 0.35 μm CMOS technology is presented for low operating voltages. The increased reliability margin at low supply voltages was used to scale the gate oxide thickness and optimize the channel and source/drain junctions profiles. The resulting well controlled short-channel behaviour of the devices was used to obtain low leakage current at low threshold voltages. Good circuit performance...
Charge pumping of single interface traps in small area MOSFET's is demonstrated for the first time. The dependence of the single trap charge pumping current on the base level voltage is described. Also the creation of one single interface trap under influence of low level hot carrier injection is demonstrated. The correlation with RTS-noise experiments is discussed.
Substrate hot hole injection was used to investigate hole trapping in thin oxides of MOS transistors. It has been found that tunnelling hole injection into the oxide may take place at hole energies much lower than that needed for over-the-barrier emission. Resulting threshold voltage shift and hole detrapping kinetics during subsequent high-field electron injection indicate different amount and distribution...
The Philips compact MOS model, MOS MODEL 9, has been developed for the simulation of analogue circuits. With only 18 parameters mos MODEL 9 describes accurately the characteristics in the operating regions most important for analogue design [1,2]. Recently the capabilities of the model in describing various processes, with minimum channel lengths as low as 0.35 ??m, have been presented [1]. MOS MODEL...
The influence of incorporating Chemical Mechanical Polishing for pre metal planarization in a sub micron CMOS process on several electrical and structural parameters was studied. It was found that the sheet resistance is increased by a small amount. Another effect was a downward shift of the threshold voltage of the Metal-1 parasitic devices. This effect was not related to CMP, but to the removal...
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