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Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying...
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2 - 6 degree tilted off-axis (110) channel were reported. The transconductance of p-MOSFET with off-axis channel was significantly degraded compared with that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved compared with that of normal channel. The changes were larger than those observed...
Source/Drain (S/D) engineering in Ge MOSFETs is a complex interplay of various factors, including ion implantation and annealing conditions, electrical activation, the defectiveness of the starting substrate and the contact technology. Some of these aspects will be covered in the following manuscript. It is shown that the formation of highly n-type doped S/D regions suffers from a concentration-enhanced...
Future devices will be fabricated with high-k/metal gate stack and possibly employ 3D devices and/or high mobility channel materials. Gate stack research targeted for devices scaled to 32 nm and beyond should address the compatibility with scaled CMOS technologies in addition to the EOT scaling of High-K dielectric itself. This paper discusses recent progress and challenges in high-k dielectric for...
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