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Based on 3D statistical device simulation, the impacts of key statistical variability (SV) sources (in both individual and combined forms) on device characteristics are studied in detail for a 32 nm thin-body SOI technology. The corresponding impacts on SRAM cell stability are presented as well. The simulation results indicate that thin body architectures are not only resistant to random discreet...
A semi-empirical analytical model of the turn-on characteristics of poly-silicon thin-film transistor (TFT) with considering kink effect is presented based on the physical characteristics of poly-silicon thin film. With reference to the approach of modeling the kink effect in SOI devices and considering the grain boundaries in poly-silicon thin film, the dc characteristics of poly-silicon TFT are...
Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying...
This paper reports an analysis of the STI-induced mechanical stress-related breakdown characteristics of the 40 nm PD SOI NMOS device with a closed-form formula. As verified by the experimentally measured data, the 2D simulation results and the closed-form formula, the breakdown voltage becomes higher for the device with a smaller S/D length of 0.17 ??m due to the weaker function of the parasitic...
In this work, the impact of strain engineering on device performance and reliability for FUSI-gate SOI CMOSFET was investigated. With electrical measurement and reliability inspection, we found that there is similar enhancement on device performance, but different endurance on stressing induced device degradation for n/p MOSFET in respectively. Related noise analysis as well as charge pumping techniques...
Based on the exact resultant solution of two dimensional Poisson equation, a new analytical subthreshold behavior model consisting of two dimensional potential, threshold voltage and subthreshold swing for the dual material gate (DMG) SOI MESFETs is developed. The model is verified by the good agreement when compared with the numerical simulation of device simulator MEDICI. The model not only offers...
In this paper, an analytical model is proposed to study the carrier recombination-generation (R-G) processes in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFET's). The correlations of the carrier lifetimes and the external perturbation rates have been investigated to examine the applicability and accuracy of techniques for carrier lifetimes measurement in device...
Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process, the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and reliability. Even for ideal strained Si on SOI substrates, the impacts of various CMOS process steps, e.g., patterning, oxidation,...
Rising demand for computing, mobile and telecommunication applications has fueled increasing efforts to integrate analog and digital functions on a single chip to create System-on-Chip (SOC) type applications. To improve RF performance of devices alternate structures must be explored to overcome problems such as degrading ROUT and gain, parasitics, noise and linearity. Towards this end, novel asymmetric...
A novel quasi-silicon-on-insulator (quasi-SOI) flash memory cell is proposed for the first time. By utilizing quasi-SOI structure, program/erase (P/E) performance improvement is achieved due to the enhancement of electric field in the injection region, compared with conventional cell structure. Moreover, the off-state current at large drain bias is greatly reduced by 2 orders of magnitude with the...
In order to verify RF front-end single-chip solution, we have demonstrated several design cases for both Power Amplifier (PA) cells using SiGe HBTs and RF Switches (RFS) using CMOS technology on SOI. The PA-cell packaged has achieved 28 dBm linear output power with 36.2% PAE and more than 9.1dB gain at 836 MHz and 3.6 V. The PA-cell passes VSWR=10:1 ruggedness test at 4.2 V. With more on-wafer loadpulled...
A new SOI LIGBT structure with a combination of uniform and variation in lateral doping profiles on partial membrane (UVLD PM SOI LIGBT) is proposed in this paper. Its silicon substrate under the drift region is selectively etched to remove the charge beneath the buried oxide so that the potential lines can release below the membrane, resulting in an enhanced breakdown voltage. Moreover, combining...
A self-aligned novel S/D tie SOI device is presented for the first time in the field of silicon on insulator technology. The new device having thick-body and body-passway is demonstrated to improve the self-heating effect and decrease the parasitic source/drain resistance. When the source/drain-tie length is too small or too big, the negative differential conductance behavior can be observed. It can...
This work studies the analog performance of uniaxially and biaxially strained single-gate fully depleted SOI nMOSFETs and standard and strained Si (sSOI) n-type triple-gate FinFETs with high-?? dielectrics and TiN gate material. The analysis is performed focusing on some important analog figures of merit such as transconductance, Early voltage, output conductance and intrinsic voltage gain. It is...
In this study, the design and typical applications of an isolation feedback generator circuit were presented. The circuit was processed in 40 V SOI bipolar process technology, and integrated the precision reference source, the high-frequency oscillator, the error amplifier, and the complete modulation module, and simplified the design of the isolation and closed-loop feedback of primary switching...
This paper proposes a new self-aligned process to form the silicon-on-insulator with block oxide. Based on the TCAD simulation, we have proved that the new process can get excellent short-channel effects immunity compared to the previous process [1]. Also, the new process can overcome the problem of the previous one, which can not be used on the thin BOX devices, so that the application of the block...
FD SOI MOSFETs with MESA and Irradiated FD SOI MOSFETs with LOCOS isolation usually show the edge effect, that is, the leakage current called hump is generated in the subthreshold region. According to different reasons for generating the edge effect, rounded corner process and BTS structure are applied to improve device performance. The results indicate that the above two methods are effective to...
Reduced Bulk Field (REBULF) technology is used in the design of lateral power devices to improve breakdown voltage. Since this technology was firstly presented in 2006, this technology has gained widespread attention amongst researchers and has shown to offer good performance in a variety of application domains, especially in bulk silicon and SOI. This paper aims to offer a compendious and timely...
Speculative SPICE models (also referred to as evaluation-level or guess models), which are extracted based on projected device electrical characteristics (called `targets??) rather than actual measurement data, are required to support concurrent IC designs. The self-heating effect in silicon-on-insulator (SOI) technologies presents additional challenges in obtaining quality speculative SOI MOSFET...
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