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The computational complexity and hardware design of block-matching criteria were discussed, and a novel MPDC algorithm and its VLSI structure for H.264 were presented, in which a QP adaptive MPDC threshold was derived from the basics of H.264 4??4 integer transform and 52-level scalar quantization and the calculation process was adjusted for hardware optimization. When QP is greater than 18, the proposed...
This article summarizes the history and progresses on our development of the Bipolar Field-Effect Transistor Theory (BiFET). The 2-Dimensional (2-D) rectangular geometry of the transistor (uniform in the width or Z-direction) is employed to decompose the 2-D equation into two 1-D equations which are parametrically coupled by the surface-electric-potential. This decomposition enables us to obtain the...
We present a historic overview of the initial motivating ideas, original foundations, and subsequent development, of integration-based methods which are currently used to extract semiconductor device model parameters, as well as to assess devices?? and circuits?? non- linearity. To illustrate these methods?? capabilities, in this paper we review sample applications specifically focusing on two-terminal...
The paper presents a comprehensive study of Spice modeling for some key physical effects observed in a 65 nm CMOS process. STI-induced stress effect, well proximity effect, as well as HCI and NBTI reliability effects, which can not be neglected for technologies beyond 90 nm and must be properly modeled for accurate circuit simulations, are discussed in this study.
Model order reduction by truncated balanced realization (TBR) is better than Krylov subspace methods to achieve smaller models with global error control. TBR projects a system onto the dominant invariant subspace in terms of both controllability and observability measured by their gramians. However, to obtain two gramians, two Lyapunov equations have to be solved and its high computation costs involved...
This paper presents a solver to build macromodel of cell-based logic block for hierarchical power distribution network analysis. It first reduces logic block circuit model with circuit combination and capacitor equivalent transformation, and then build macromodel by the method of equivalent circuit. At last, node voltages are calculated by back solving. By building logic block macromodel, computation...
As one of the candidates of the next generation non-volatile memory (NVM), phase change memory(PCM) has been paid more attention. But there are many open issue in simulation and phase-change mechanism. In this work, an electrothermal simulation is implemented, which can provide an evaluation method for PCM geometry and scaling design. At the time, a threshold-switching mechanism is discussed. A threshold-switching...
This paper reviews recent development on compact modeling of multiple-gate MOSFETs. First, a core model based on the analytic potential solutions for the highly symmetric double-gate (DG) and surrounding-gate (SG) MOSFETs has been presented. With the addition of quantum, short-channel effects, and capacitance formulations, the core model for DG MOSFETs has been expanded into a full-blown compact model...
A novel quasi-silicon-on-insulator (quasi-SOI) flash memory cell is proposed for the first time. By utilizing quasi-SOI structure, program/erase (P/E) performance improvement is achieved due to the enhancement of electric field in the injection region, compared with conventional cell structure. Moreover, the off-state current at large drain bias is greatly reduced by 2 orders of magnitude with the...
One-dimensional model is developed and solved numerically to investigate the flow of liquid and vapor in triangle grooves. The effect of liquid and vapor interfacial shear stress is taken into account in this model that can greatly improve the accuracy of the results. The results obtained from this simulation contain behaviors of pressure and flow patterns, the effect of different working conditions...
This paper designs a 64-bit floating-point reciprocal and square root reciprocal unit of a stream processor (FT64), which combines the methods of table look-up and functional iteration to implement division and square root operations. This unit which is implemented with two pipeline stages provides the initial value for the iteration of division and square root. A semi-custom and full-custom mixed...
This paper presents a compact power efficiency model to be applied in the analysis and design of clock overlapping of four-phase Dickson charge pump. The hands in equations on the optimal clock overlapping are concluded. Based on 0.25 um CMOS technology, the proposed model is consistent with the simulation result. Both simulation and model validate the optimal clock overlapping range attains better...
Inverse Lithography Technology (ILT) is a promising solution to enhance the resolution of the optical system in deep-subwavelength lithography. In this paper, we introduce a gradient-based framework for mask synthesis. Firstly, we model the mask-to-wafer process using a continuous transfer function. Then Newton iterations are employed to solve the continuous inverse problems. Finally, we apply our...
Solvers based on a spherical harmonics expansion (SHE) of the Boltzmann equation (BE) are a deterministic alternative to the stochastic Monte Carlo (MC) method. Their numerical properties are very similar to the classical approaches (drift-diffusion or hydrodynamic models), and the same numerical methods can be used (box integration, maximum entropy dissipation scheme (MEDS), Newton-Raphson method,...
A complete surface potential-based current-voltage and capacitance-voltage core model for cylindrical undoped surrounding-gate (SRG) MOSFETs is presented in this paper. This model allows the current-voltage (IV) and capacitance-voltage (CV) characteristics to be adequately described by a single set of the equations in terms of the surface potential. The model is valid for all operation regions and...
In this paper, an empirical truncated balanced realization (TBR) approach is introduced to reduce the model order of non-quasi-static (NQS) effects in MOSFETs. In the PSP model (an industrial standard in compact modeling of MOSFETs), a simple spline-collocation (SC) approach is most commonly used to compute NQS. The SC technique, however, suffers from relatively high computing effort. To the best...
This paper studies the error of the hybrid filter banks (HFB) due to analog realization errors. Small errors have a dramatic influence on the aliasing and distortion functions of HFB. The performance deteriorates with the error of analog devices growing. The simulations show that the aliasing and distortion errors based on power complementary pairs (PCP) are much lower than conventional HFB ADCs??...
A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by...
Based on the equivalent Elmore delay model, a new delay model that takes inductance and thermal effect into consideration is presented in this paper. The proposed model with high efficiency has closed-form expression. Its solution exhibits high accuracy as compared to the other models. Simulation results show that the error in the propagation delay is less than 10% for RLC tree example.
A voltage doubler, which avoids body effect and then improves rise time and efficiency even with 1 V power supply, is presented. This art is designed for word line boosting, using 0.18 um EEPROM technology. Not only the voltage doubler can work with capacitive load normally, but also it can supply load current and achieve higher efficiency. The whole circuit can be implemented on chip and is suitable...
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