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In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal...
The paper presents a comprehensive study of Spice modeling for some key physical effects observed in a 65 nm CMOS process. STI-induced stress effect, well proximity effect, as well as HCI and NBTI reliability effects, which can not be neglected for technologies beyond 90 nm and must be properly modeled for accurate circuit simulations, are discussed in this study.
A novel bandgap reference for minimizing current-mirror mismatch is presented. In the proposed circuit, the small-signal current variations in the two current paths are self-compensated while in the conventional bandgap core they are multiplied. As a result, error caused by current-mirror mismatch has been much reduced in the proposed circuit. Moreover, the voltage variations caused by temperature...
Three-dimensional integrated circuit (3D IC) is emerging as an attractive option for overcoming the barriers in interconnect scaling, thereby offering an opportunity to continue performance improvements using CMOS technology. 3D IC offers the advantages of high performance, low power, smaller form-factor, and heterogeneous integration benefits. However, to enable the wide adoption of the 3D integration...
Model order reduction by truncated balanced realization (TBR) is better than Krylov subspace methods to achieve smaller models with global error control. TBR projects a system onto the dominant invariant subspace in terms of both controllability and observability measured by their gramians. However, to obtain two gramians, two Lyapunov equations have to be solved and its high computation costs involved...
This paper presents a solver to build macromodel of cell-based logic block for hierarchical power distribution network analysis. It first reduces logic block circuit model with circuit combination and capacitor equivalent transformation, and then build macromodel by the method of equivalent circuit. At last, node voltages are calculated by back solving. By building logic block macromodel, computation...
A charge based compact model with self-heating effects has been developed for LDMOS transistors. Both the channel and drift regions in LDMOS are modeled without adding an internal drain node. An efficient scheme for including self-heating effects is implemented in the model, which requires no thermal network. A comparison with measured data from an LDMOS shows that the model has excellent accuracy...
This paper proposes a quaternary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%, an interconnection reduction of 25.0%, and a power-delay-product reduction of 43.1%. Therefore, this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness...
This paper designs a 64-bit floating-point reciprocal and square root reciprocal unit of a stream processor (FT64), which combines the methods of table look-up and functional iteration to implement division and square root operations. This unit which is implemented with two pipeline stages provides the initial value for the iteration of division and square root. A semi-custom and full-custom mixed...
The scaling of CMOS technology intensifies the interaction between design and process at 45nm or below, causing strong layout-dependent proximity effects. Photolithography, strain silicon engineering, and ion implantation are the primary causes of those effects, whose impacts to design can be mitigated via restrictive design rules and accurate modeling. A novel approach is proposed that seamlessly...
Mechanical vibration energy can be converted into electrical energy using piezoelectric power generator. The electrical energy is usually collected by a storage capacitor instead of being directly consumed by the load. In this way, to characterize the charging of the storage capacitor is important and necessary. This paper focuses on the characterization of the piezoelectric power generator with capacitive...
In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15%...
The dead lock problem of conventional SAR DLL is discussed. Different improvement approaches to fix the dead lock problem of conventional SAR DLL are shown and compared. A new improved SAR controller whose relock-in steps are only 2 k is proposed in this paper. Its relock-in process is illustrated. Verification of this new SAR controller is done by Hspice simulation.
A kind of arithmetic and its implementation of bit-stream adder which can be used in digital signal processing were discussed in this paper. Compared with multi-bit adder, the bit-stream adder has the advantages of much simple structure and much small routing area. The ideal circuit model of the bit-stream adder was improved with a pipe line structure to make it work correctly in high frequency range...
This paper presents an interface circuit for CMOS-MEMS gyroscope using integrated diode-rings. A brief introduction for the CMOS-MEMS integration technology [1] using high-ratio isolation trench will be introduced first. The integration system contains a Z-axis capacitive bulk silicon gyroscope and an interface circuits using diode-ring doing the first demodulation. A detailed analysis for the integrated...
This paper describes a low swing differential signaling scheme for on-chip global interconnects. A simple MOS current mode logic circuit is used to provide an attractive alternative to conventional full swing voltage signaling. The most traditional low swing drivers use additional reference voltages to limit the signal swing. By applying the proposed circuit, a low voltage swing of 110 mV can be obtained...
Interconnection parasitic capacitance is the dominant delay and noise source in modern integrated circuits. This paper presents a test structure and a characterization method based on charge based capacitance measurement technique. The method could be implemented to study the variability of physical parameters such as interlayer dielectric (ILD) thickness and interconnect drawn width reduction, which...
A reduced, canonical, weighted generalized list (WGL) is presented in this paper. This representation can effective describe world-level polynomial function. The reduction rules of WGL were proposed, and the equivalence verification method of register transfer level (RTL) design based on WGL was implemented. Experimental results show that WGL is more effective than other existent model, when it is...
Multi-threshold CMOS (MTCMOS) technology provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with MTCMOS technology. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest...
Most integrated circuit ESD damages are caused by CDM stresses. This paper discusses CDM failure modes. The most common such failure is damage to the gate oxide in the MOS device. A new methodology that uses a gate oxide damage monitor and modified VFTLP testing is proposed for assessing CDM protection effectiveness and robustness in I/O circuits. A test structure for such an evaluation is also introduced.
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