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We fabricated a carbon nanotube (CNT) via interconnect and evaluated its electrical properties. We found that the CNT via resistance was independent of temperatures, which suggests that the carrier transport is ballistic. From the via height dependence of the resistance, the electron mean free path was estimated to be about 80 nm, which is similar to the via height predicted for hp32-nm technology...
65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch...
Three-dimensional integrated circuit (3D IC) is emerging as an attractive option for overcoming the barriers in interconnect scaling, thereby offering an opportunity to continue performance improvements using CMOS technology. 3D IC offers the advantages of high performance, low power, smaller form-factor, and heterogeneous integration benefits. However, to enable the wide adoption of the 3D integration...
Practical aspects of synthesis and applications of single-wall and multi-wall carbon nanotubes (SWNT and MWNT, respectively) are presented. Among numerous potential applications, utilization of nanotubes for interconnections in microelectronics and in gas sensors is considered in more detail. The issues related to compatibility of nanotubes synthesis and manipulation processes with the Si planar technology...
With the complementary metal-oxide-semiconductor (CMOS) technology approaching its scaling limit, many novel devices and material are being considered to enable further scaling of CMOS. Carbon nanotubes show unique properties and are currently considered as a potential alternative material for nano-CMOS building blocks. Performance of carbon nanotube field effect transistors (CNFET) can be competitive...
Current-induced breakdown phenomena of carbon nanofibers (CNFs) for future on-chip interconnect applications are presented. The effect of heat dissipation via the underlying substrate is studied using different experimental configurations. Scanning electron microscopy (SEM) techniques are utilized to study the structural damage by current stress. While the measured maximum current density in the suspended...
The recently presented new theory of electromigration of metal atoms is summarized. The new theory attributes the migration to diffusion of electrical neutral atoms and generation-recombination-trapping of the electrically neutral atoms in the bulk of the metal line and on the interior surfaces of the voids in the metal line. It assumes no drift current or zero host ion current, and it asserts no...
This paper proposes a quaternary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%, an interconnection reduction of 25.0%, and a power-delay-product reduction of 43.1%. Therefore, this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness...
This paper presents a cell-based modeling and design platform for high-frequency analog ICs to shorten design cycle time and to minimize the risk for mask re-spin. Based on a pre-characterized analog sub-circuit cell library, which contains not only active devices and passive components but also routing interconnects. This methodology systematically alleviates modeling inaccuracy at high frequencies...
Metal ions embedded in dielectric films may play an important role in the reliability of advanced interconnect systems. In this talk, we will discuss the generation and drift of different metal ions such as Cu, Ta, and Ti into the dielectric materials from gate electrodes under an external electric field at elevated temperatures. Some strategies to eliminate the generation of metal ions will also...
MOSFET scaling has served our industry well for several decades by providing significant improvements in performance, density and power, but traditional MOSFET scaling has run into hard roadblocks. Interconnect and patterning technologies have also run into significant limitations when trying to follow traditional scaling methods. The past few years have seen the introduction of new materials and...
Inductive effect becomes important for on-chip global interconnects, like Power/Ground (P/G) grid. Partial reluctance (the inverse of partial inductance) has been accepted to model inductive effect, for its local property. In this paper, a new method which makes full use of the structure regularity of P/G grid is proposed. With a reuse scheme and carefully handling of boundary effect, the proposed...
Static-random-access-memory(SRAM)-based field programmable gate arrays (FPGAs) consists of 50% ~70% routing resources. A simple programmable interconnect point (PIP) is a switch controlled by SRAM configuration cell connecting two wires. A novel traverse algorithm targeted for the detection of PIP open faults is proposed. Experimental results run on the Fudan design system (FDS) platform show that...
This paper presents a novel application-dependent interconnect testing scheme for Xilinx FPGAs. In this scheme, the interconnects in FPGAs' application configuration (AC) are decomposed into line branches, and the targeted line branches are partitioned into multiple subsets so that the CLBs' test configurations required to test the line branches in each subset are compatible. Multiple test configurations...
Carbon Nanotube (CNT) interconnects provide one of the most promising on-chip interconnect techniques for future VLSI systems, although significant process and runtime variabilities remain challenging for CNT interconnects. In this paper, we propose a performance variation adaptive differential signaling scheme, particularly for carbon nanotube bundle on-chip interconnects. Estimation based on published...
This paper presents the fundamentals and recent progresses of 4-port based error correction and parasitics de-embedding techniques we developed for high frequency transistor measurements. RF CMOS data from 2 to 110 GHz will be shown to illustrate various techniques.
In this paper, we propose a novel on-chip global interconnect that would meet stringent challenges of core-to-core communications in data rate (up to 100 Gbps /link), latency and re-configurability for future chip-microprocessors (CMP) with efficient area and energy overheads. We discuss the limitations of traditional RC-limited interconnects and possible benefits of multi-band RF-interconnect (RF-I)...
Based on the equivalent Elmore delay model, a new delay model that takes inductance and thermal effect into consideration is presented in this paper. The proposed model with high efficiency has closed-form expression. Its solution exhibits high accuracy as compared to the other models. Simulation results show that the error in the propagation delay is less than 10% for RLC tree example.
In this paper, the equalization techniques for high-speed interconnect transceivers are discussed. Serial interconnect transceivers have been widely adopted for its high data transfer rate, low cost, good noise immunity and low EMI. Signal SNR can be severely degraded by transmission channel. Effects due to channel impairments and tradeoffs among different equalization techniques are discussed in...
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