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We present an overview and electrical results for a novel deep trench decoupling capacitor. The process of this decoupling capacitor borrows from the regular embedded DRAM trench process, but with significant process simplification for decoupling use which provide reduced cost and reduced process cycle time. This capacitor can provide significant chip-level area savings, using only 1/8 silicon real...
65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch...
We investigated the growth of crystalline ZrO2 film prepared on p-Si(100) by limited reaction sputtering system under different growth temperatures from 400 to 700??C. The structural characteristics of the samples were studied by XRD, RHEED and AFM, which provided a solid identification of the phase transformation from monoclinic phase to tetragonal phase. The dielectric properties were studied by...
We present a study of optical characteristics in visible and vacuum ultra-violet range of porous low-k dielectric films (prepared by chemical vapor deposition), and the constituent materials: Carbon doped oxide (SiCOH) matrix and organic porogen. The materials have been deposited as thin film samples and cured by thermal annealing and UV irradiation for various times. The optical properties of the...
By depositing a PMMA (poly(methyl methacrylate)) layer on top of an evaporated layer of ZrO2, the leakage has 4 orders of magnitude reducing compared with bare ZrO2 layer. Low roughness of PMMA/ZrO2 surface produces a high quality interface between the organic semiconductor and the combined insulator, thus the device has a significant improvement in performance. The typical field effect mobility,...
A novel digital microfluidic device using the high dielectric constant material P(VDF-TrFE) (poly-vinylidene fluoride-trifluoroethylene) as the dielectric layer fabricated by spin-coating process is proposed. The device is featured with the advantages of both low driving voltage and IC compatible process. The dielectric constant of P(VDF-TrFE) is measured as high as 11.6. The contact angle between...
In this paper, a novel power device named as RESURF Dielectric Inserted (REDI) LDMOS is put forward. It is fully compatible with standard CMOS technology, which can sharply reduce the cost. In this novel REDI LDMOS, a RESURF structure and a dielectric region are inserted at the suitable position of the drift region to reconstruct the electric field and the electric potential distributions of the channel...
LaAlOx with a permittivity of 17 is fabricated successfully by ALD method. Enhanced deposition rate, improved uniformity and self-limiting behavior were observed for LaAlOx compare to La2O3 deposition. The mechanism behind improvement is proposed. ALD LaAlOx is found to be thermally stable up to 850??C anneal. Compared with Al2O3 blocking oxide control samples, the SONOS devices with LaAlOx blocking...
In this work, the surface and interfacial properties of the ultra-thin HfO2/SiO2 gate stack dielectrics fabricated on the p-type Si (100) substrates by atomic layer deposition is studied. Grazing incidence x-ray diffraction result manifests the HfO2 film is almost ideal amorphous phase. Atomic force microscopy images reveal that the surface roughness of the HfO2 is extremely small and the surface...
ALD, as a state-of-the-art oxide formation technique, provides unprecedented opportunity to study various deposited oxides or insulators on III-V materials. The interface property of oxides or insulators on III-V compound semiconductors is a very complex problem. The underlying reasons for these above experimental observations mostly are not well-understood. To find an excellent dielectric and gate...
Evidence of mobile, positive charges (holes) on the top surface of GaN HFET is found by conducting C-V measurement of a MIS HEMT diode. Significantly improved understanding of the effects of built-in electric polarization and doping on III-nitride heterojunction device structure electrical properties has been made. The result also confirms that removal of surface mobile holes is the root cause for...
In this work we propose an analytical model for the gate current 1/f noise in CMOS devices. The model is based on a simple idea: one electron trapped in the dielectric switches-off the tunneling through the oxide over an effective blocking area. The model allows evaluating the effective trap density inside the gate dielectric as a function of energy from measurements of the gate current 1/f noise...
A novel capacitive temperature sensor based on multilayer cantilevers is presented. The top and bottom layers are metal and heavily boron doped Si, respectively. A combined SiO2/Si3N4 layer is utilized as the elastic dielectric layers of the sandwich multilayer cantilever. The operation principle of the structure is based on the effect of thermal expansion coefficient mismatch and the available physical...
The device characteristics and manufacturability of ultra-thin oxynitride have been systemically studied in this paper for CMOS applications. We have found that the transistor with plasma oxynitride gate dielectrics gives better pFET performance in terms of drive current, mobility, threshold voltage and leakage current as compared to the one with thermal oxynitride. For nFET, the performance for transistors...
The solid-state reaction of Ni/Si in the presence of other elements is investigated. The alloying effects on both NiSi/Si Schottky contacts and Ni fully silicided (FUSI) gates on SiO2 dielectric are studied by phase, composition, and electrical characterization tools. The results show that after silicidation Er, Y, and Al all segregated at the Ni-silicide surface rather than piled up at the Ni-silicide/Si...
The thin gate dielectric behavior for CMOS devices was investigated. The linear correlation of thickness measured by optical and XPS can still work for ultrathin gate oxide with thickness less than 10 angstrom. Electrical properties, including EOT, NBTI, mobility and Ion-Ioff, were strongly correlated with nitrogen concentration within oxide and the oxide thickness measured by XPS. It is the purpose...
Plasma-based technologies such as plasma immersion ion implantation and deposition (PIII&D) are widely used. In addition to the capability to alter the materials surface, novel microelectronic structures can be fabricated. In this invited paper, our recent research activities on the application of plasma technologies to microelectronics are reviewed. Silicon-on-insulator (SOI) is replacing conventional...
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