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This paper describes the design and test results of a high performance low noise amplifier (LNA) for code division multiple access (CDMA) one chip transceiver integrated circuit (IC). The circuits are implemented in a standard 0.35-um Samsung Si/Ge BiCMOS process. The LNA has 4 step forward gain control of 15.8 dB, 4 dB, -7.5 dB, and -21 dB. The measured performance of the proposed LNA at the maximum...
A comparison between lattice matched (lm) and pseudomorphic HEMTs (pHEMTs) aimed for cryogenically cooled low-noise amplifiers (LNAs) has been performed. The DC and RF performance of the HEMTs at room temperature (RT) has been investigated. The devices have been tested in a hybrid 4 - 8 GHz LNA. While the gain and noise were superior for the pHEMT compared with the lm HEMT at RT, the noise performance...
A low-power-consumption (26.93 mW) 32-GHz (Ka-band) low noise amplifier (LNA) using standard 0.18 mum CMOS technology is reported. To achieve sufficient gain, this LNA is composed of three cascaded common-source stages. The output of each stage is loaded with a band-pass (or a high-pass) combination of L and C to provide parallel resonance, i.e. to maximize the gain, at the design frequency. This...
This paper describes a 1.5-V 2.4 GHz variable gain front-end in a 0.18-mum CMOS process. The front-end achieves conversion gains of 27.0 dB and 15.0 dB in the high gain mode (HGM) and low gain mode (LGM), respectively. It also achieves input return loss, Sn, of -10.18 and -15.31 dB in the HGM and LGM, respectively. In the HGM and LGM, the front-end acquires double side band (DSB) NFs of 4.0 dB and...
A dual-band low noise amplifier (LNA) which can operate at both 2.4GHz and 5.2GHz frequency band is proposed. Input matching, noise matching and narrow gain are achieved at 2.4GHz and 5.2GHz frequency band by switching the equivalent inductance and resistance of input and output circuits. The proposed LNA is designed in a TSMC 0.18um CMOS technology with a supply voltage of 1.5V. The LNA has gain...
This paper presents the design and simulation of a CMOS Ultra-wideband Low noise Amplifier. In the design, specific architecture decisions were made in consideration of system-on-chip implementation. The basic architecture of the LNA designed herein exhibits a differential amplifier core with active input and output impedance matching. Simulations reveal that the LNA maintains a gain of 16.7 dB with...
An ultra-wideband (UWB) 3.1-4.8 GHz radio front-end consisting of three frequency multiplexed antennas and a low-noise amplifier (LNA) is presented in this paper. Using one antenna for each sub-band and an LNA designed for maximum-flat power gain provides equal performance within the entire frequency band. Frequency multiplexing is used to combine the antennas for multi-band UWB. The LNA is optimized...
This work presents a fully integrated differential 5.8 GHz low-noise amplifier (LNA). The LNA is fabricated in a 90 nm RF-CMOS process and has a power gain of 12.5 dB, an IIP3 of 4dBm, and a noise figure of 1.7 dB consuming 14 mA from a 1.2 V supply. Compared to previously reported differential CMOS designs this LNA show lower noise figure and better linearity.
This paper presents an ultra-low voltage UWB LNA in a commercial 0.18mum CMOS technology. The technique of inductive degeneration is used in a two-stage conventional distributed amplifier to achieve broadband and low noise. The common source single-stage amplifier is cascaded to the conventional distributed amplifier to improve the gain at high frequency. The measured gain of the integrated LNA is...
A 1.6 GHz CMOS single-ended low noise amplifier (LNA) optimized for integration and use in Global Positioning System (GPS) applications is presented. The LNA is implemented in a 0.13 mum standard CMOS process with on-chip inductors. The LNA achieves a noise figure of 1.35 dB, a power gain of 16.7 dB and a 1 dB compression point of -14 dBm at a current consumption of 8.5 mA from a 1.8 V supply. The...
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