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This paper introduces a new flow able to lit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. The flow is based on iterative refactoring and transformations of the application. From the resulting application, a VHDL code is generated. This code is finally used to simulate or synthesize the application. Significant experiments have validated...
A novel routing fabric is introduced that offers high flexibility at significant lower silicon cost compared to routing fabrics currently incorporated in many field programmable gate array (FPGA) devices, IP cores, and IP-core wrappers. The novel fabric is entirely constructed from multiplexers and unidirectional point-to-point connections, controlled by configuration bits, and prove very efficient...
Currently, the hardware and the software tasks in reconfigurable systems are either scheduled separately at run time or co-scheduled statically, which results in high power consumption and low performance. This work proposes runtime co-scheduling of hardware and software tasks by using the slack time, which is introduced due to reusing hardware task configurations, for dynamically scaling the processor...
This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the salt-and-pepper noise of high intensity (up to 70% of corrupted pixels). The proposed solution combines image filters designed by means of evolutionary algorithm with a simple human-designed preprocessing and post-processing unit. It provides the same filtering capability as a standard adaptive...
This paper presents significant improvements to our previous watermarking technique for Intellectual Property Protection (IPP) that enables the protection of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using combinational logic included within the original system. Thus, any attack trying to change or remove the digital signature will damage the...
Numerical non-robustness is a recurring phenomenon in scientific computing. It is primarily caused by numerical errors arising because of fixed-precision arithmetic in integer and/or floating-point computations. Exact computation, based on arbitrary-precision arithmetic, has been developed over the last decade as an emerging numerical computation paradigm in response to this problem of numerical non-robustness...
FPGA is currently a very important design technology to implement electronic systems due to its high logic density, its fast time-to-market and its low cost. But in order to provide high logic density FPGA devices are fabricated with nanometer CMOS technology that is becoming susceptible to radiation-induced soft errors. Among these errors, single-event transients (SETs) are those that are induced...
We describe the optimization of power consumption obtained by a high level environment developed for the automatic generation of application specific circuits on FPGA. The methodology used is based on the transformation of the whole algorithm in a graph of LUTs that implements all the required operations without the use of library components. The quality of the obtained circuitry is guaranteed by...
In this paper we present an FPGA-based dataflow architecture that both efficiently computes parallel algorithms using dedicated FPGA resources and scales well to multi-FPGA chip designs while the overall communication bandwidth increases. The basic idea is based on reconfiguration. In contrast to the concept of partially reconfiguring FPGAs, our approach is to connect computational units via a dynamically...
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPR0 for placement and routing on 3D FPGAs and (ii) the 3DPower for power/energy estimation on such architectures. We mainly focus our exploration on the total number of layers and the amount of vertical interconnects (or vias). The efficiency of the proposed...
The effect of kernel operations on cache optimisations in a soft-core reconfigurable system is important for dynamic cache switching design. Considering kernel operations changes the subset of cache configurations that would be chosen for dynamic cache switching and also the decisions on when to cache switch. The results show that kernel operations can skew the effectiveness of application driven...
WSAT and its variants are one of the best performing stochastic local search algorithms for the satisfiability (SAT) problem. In this paper, we propose an FPGA solver for very large SAT problems based on a WSAT algorithm. In our solver, parallel and multi-thread processing are combined (1) to fully utilize parallel accesses to external memory banks, and (2) to enhance the utilization of internal memory...
Several examples have shown that adaptive computers are capable of outperforming traditional workstations in terms of computing time as well as energy efficiency. Developing applications for an adaptive computer, however, is often a complex task. Hardware (HW) and software (SW) parts as well as their interfaces have to be implemented, requiring specialized skills as well as additional design time...
Multiple sequence alignment problems in computational biology have been focused recently because of the rapid growth of sequence databases. By computing alignment, we can understand similarity among the sequences. In this paper, we describe a compact system with an FPGA board and a host computer for multiple sequence alignment based on Carrillo-Lipman method. In our system, two dimensional dynamic...
In particular for applications where no repair is possible, e.g. space missions, high reliability is usually an important requirement. Long mission times and harsh environment are a challenge for electronic circuits, and particular error mitigation techniques have to be implemented in order to be able to cope with the expected error effects. Our approach instead is based on delay-insensitive asynchronous...
We present a new De-Blocking Filter module fully optimised for use on a recently introduced dynamically reconfigurable, instruction cell based architecture. The module consists of a novel combination of standard software transforms alongside architecture specific techniques and aims to reduce reconfiguration overheads and increase utilisation of resources. Our proposed filter outperforms the standard...
This paper introduces a scalable FPGA implementation of a stochastic simulation algorithm (SSA) called the next reaction method. There are some hardware approaches of SSAs that obtained high-throughput on reconfigurable devices such as FPGAs, but these works lacked in scalability. The design of this work can accommodate to the increasing size of target biochemical models, or to make use of increasing...
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analysis of the program's dataflow graphs. The characteristics of certain applications and the modern compiler optimization techniques (e.g., loop unrolling, region formation, etc.) have lead to substantially larger dataflow graphs...
This paper introduces an algorithm for DNA string detection and proposes its efficient hardware implementation on FPGA devices. Its main application field is intended to be the detection of intron and exon strings in DNA chains, but its applicability is not limited to Genetics. The GenDiv algorithm is based on the dynamic programming method. For the software implementation, the algorithm's complexity...
Knowing the capacitance of circuit nets in an FPGA design is essential when computing the dynamic power consumed by switching these nets. Before a circuit is placed, however, there is little information available to allow the capacitance of routing wires to be estimated. In this paper we study the feasibility of estimating routing capacitance before RTL-synthesis to allow high-level power consumption...
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