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Traditionally, logic synthesis constrains the solution space of later design steps, such as physical design, because they are applied in sequence. Rewiring is a technique to restructure a circuit while maintaining its functionality. Since design properties and objectives can be considered during post-synthesis rewiring, it can help relieve constraints put forth by decisions made at earlier design...
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel method to reduce reconfiguration time by maximising wire use and minimising wire reconfiguration. This builds upon our previously-presented methodology for creating modular, dynamically-reconfigurable applications targeted...
This paper describes an FPGA-based accelerator for maze routing applications such as integrated circuit detailed routing. The accelerator efficiently supports multiple layers, multi-terminal nets, and rip up and reroute. By time-multiplexing multiple layers over a two-dimensional array of processing elements, this approach can support multi-layer grids large enough for detailed routing while providing...
The aim of the hartes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hartes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW...
This paper focus on on-line placement and scheduling of tasks with known executing time on reconfigurable devices. The notion of recognition-earliest for scheduling algorithms is introduced, that is the algorithm can arrange the start time of a newly arrived task as early as possible. A new scheduling algorithm is proposed. By exploit the knowledge about temporal properties of each task, the algorithm...
A high performance RLS lattice filter with evaluation of an unknown order of identified system was implemented as an accelerator PCORE for Xilinx EDK. The accelerator hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programing and debugging of a hardware accelerated DSP applications. The optimal logarithmic number...
Modern FPGAs have become so affordable that they can be used to substitute ASICs in mass produced devices. A key component of such configurable system on a chip (CSoC) is the processor core. Available and usable cores are either 32 or 8 bit wide. Thus, there is a gap between these two extremes, which we want to fill with our SoC kit. In this contribution we elaborate on our SoC kit and its components...
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of power, since it connects to every latch on the FPGA and toggles every cycle, but the design of the clock network also affects how efficiently the rest of the application can be implemented since it imposes constraints on the...
The paper presents the new hardware thread interface (HWTI), a meaningful and semantic rich target for a high level language to hardware descriptive language translator. The HWTI provides a hardware thread with the same thread system calls available to software threads, a fast global distributed memory, support for pointers, a generalized function call model including recursion, local variable declaration,...
Various implementations of the quantum-dot cellular automata (QCA) device architecture may help many performance scaling trends continue as we approach the nano-scale. Experimental success has led to the evolution of a research track that looks at QCA-based design. The work presented in this paper follows that track and looks at implementation friendly, programmable QCA circuits. Specifically, we...
Modern platform FPGAs integrate fine-grained reconfigurable logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodologies have not kept up with the rise in complexity of the target hardware. In particular, there is little overlap between the programming model for embedded software running on a real-time operating system and the programming...
This paper presents a DVS (Dynamic Voltage Scaling) enabled SoC (System-on-Chip) processing platform based on the Leon3 open-source processor and dynamically reconfigurable clock synthesis technology available in Virtex-4 Xilinx FPGAs. A special DVS monitor unit maintains correct operation of the processor core at a given voltage by tracking the behavior of an internal delay line and stopping the...
This paper presents a technique to fix timing violations caused by process variations in FPGAs by adjusting the clock skews of flip-flops. This involves making the clock distribution network tunable by adding programmable delay elements to compensate for variations. We propose generic as well as chip-specific skew assignment schemes that are robust to variations. The two proposed schemes result in...
The extreme processing platform (XPP) is a new runtime-reconfigurable data processing architecture. It is based on a scalable array of coarse grained computing elements and a packet oriented communication network. The strength of XPP originates from the combination of array processing with unique, powerful runtime-reconfiguration mechanisms. Parts of the array can be configured rapidly in parallel...
Simple algorithms can be analytically characterized, but such analysis is questionable or even impossible for more complicated algorithms, such as Model Predictive Control (MPC). Instead, Monte Carlo Arithmetic (MCA) enables statistical experimentation with an algorithm during runtime for detection and mitigation of numerical anomalies. Previous studies of MCA have been limited to software floating...
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