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This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arrays (FPGAs). The feasibility of such a system is demonstrated using existing FPGAs by accelerating a cycle-based simulation of a Register Transfer Level (RTL) design description. Through the use of a common instruction set,...
The progress in hardware technologies for implementing portable, low power and low cost electronic systems for consumer products has been major the last years. The complexity of embedded systems will further increase at a rate which is not met by the development of advanced CAD tools for managing the large design space. This will likely lead to increased design problems regarding system implementation,...
This paper presents a high-speed implementation of a 2-D fixed-point discrete wavelet transform (DWT) using the embedded DSP48 blocks available on a Xilinx Virtex-4 XC4VLX15-10 FPGA. The full transform uses just 10 DSP48 blocks, 3 block RAMs and 2,126 logic elements when synthesized using Xilinx ISE Version 8.2i and can perform calculations at 197.2 MHz. The results clearly show that by using the...
In recent years, IP protection of FPGA hardware designs has become a requirement for many IP vendors. To this end solutions have been proposed based on the idea of bitstream encryption, symmetric-key primitives, and the use of physical unclonable functions (PUFs). In this paper, we propose new protocols for the IP protection problem on FPGAs based on public-key (PK) cryptography, analyze the advantages...
FPGA-based computation engines have been used as cellular automata (CA) accelerators within the scientific community for some time now. In this paper, we present a methodology to predict the performance of running such applications on a specific FPGA hardware technology before engineering the design in reality. This will help to determine the optimal values for the various parameters that control...
In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompasses both the eFPGA user and automatic layout generator perspectives. We discuss generic FPGA modeling based on VPR tool, simulation and high-level models of reconfigurable components, and we present an innovative floor-planing...
This paper presents an application specific engine dedicated for acceleration of AdaBoost image classifier. Ada-Boost and its modifications belong to the most successful algorithms of image classification. This class of algorithms can also be used for object detection through scanning of the image with a sliding window whose content is classified using AdaBoost. Such process, however, is very computationally...
This paper presents the preliminary results of a physical placement algorithm for heterogeneous Dynamically Reconfigurable Arrays (DRA), based on a multi-objective, multi-threaded GA. The algorithm deals with the spatial and temporal nature of the configurations used in DRAs, in an attempt to find a suitable layout for a wide range of applications, since general applicability is a key criteria for...
This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture is based on LUT methods and achieves lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm with a lower latency. The proposed architecture can compute the atan(Y/X) with a latency...
Symmetric encryption, secure hashing, and random number generation are essential operations for many cryptographic applications. Realizations of these functions usually aim for high computational speed. For some applications, however, low resource usage is more important. Thus, this work presents a compact design for symmetric encryption, hash function, and cryptographically secure random number generator...
The uniqueness of human fingerprints has been accepted by the scientific community since long time ago. Proof of this is the fact that, among all physiological characteristics, fingerprints are the oldest and most deeply used signs of identity for personal recognition. However up to date, the development of an automatic fingerprint-based human authentication system is an open research problem. Most...
In this work aims new techniques for mapping software loops to FPGAs. Extensive and aggressive use of pipelining techniques for achieving high performance solutions is the main goal. Those techniques are foreseen to effectively take advantage of the hardware synergies available in the current FPGA devices, especially the DSP blocks and the on-chip configurable memories.
FPGA CAD tools require wirelength predictions to make informed decisions through clustering, placement and routing stages towards power, area or delay based design goals. Unfortunately, there has been minimal work devoted to estimating individual wirelengths early in the CAD flow. Rent's rule can be used to generate a wirelength distribution but cannot be used to predict lengths of individual wires...
This paper presents a solution to safely and efficiently manage configurations of dynamically reconfigurable system on chip. We first define our unified RTOS-based framework for HW/SW task communication and configuration management. Then three issues are discussed and solutions given: the formalization of configuration space modeling including its different dimensions, the synchronization of configuration...
Most presented implementations of the exponential function confine to the single precision format. Increasing data width to the double precision format requires a different approach. The presented novel architecture employs three independent Look-Up Tables (LUTs) together with a short Taylor expansion exp(x)ap1+times. Implementation results show that the double precision exp() function implementation...
Recently, a dedicated hardware accelerator was proposed that works in conjunction with caches found next to modern-day microprocessors, to speedup the commonly utilized memcpy operation. The main assumption of the proposal was that the to-be-memcpy-ed data has to reside inside the cache, which is not always valid. In this paper, we present a dedicated load/store unit and its implementation which cooperates...
This paper describes VPF, a VLIW SIMD processor architecture developed to demonstrate the possibilities and limitations of the modern FPGA devices with respect to vector processing. VPF is developed in a bottom-up manner, using some specific Xilinx Virtex-4 device features to achieve 200 MHz performance for vector widths up to 16 issuing one VLIW instruction per clock cycle. The theoretical peak performance...
An integrated platform for fast genetic operators is presented to support intrinsic evolution on Xilinx Virtex II pro field programmable gate arrays (FPGAs). Dynamic bitstream compilation is achieved by directly manipulating the bitstream using a layered design. Experimental results on a case study have shown that a full design as well as a full repair is achievable using this platform with an average...
In this work, we present a new structure for multiplication in finite fields. This structure is based on a digit-level LFSR (Linear Feedback Shift Register) multiplier, in which the area of the digit-multipliers is reduced using the Karatsuba method. We compare our results with the other works of the literature for F397. Furthermore, we propose new formulas for multiplication in F36 97. These new...
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