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This paper presents an application specific engine dedicated for acceleration of AdaBoost image classifier. Ada-Boost and its modifications belong to the most successful algorithms of image classification. This class of algorithms can also be used for object detection through scanning of the image with a sliding window whose content is classified using AdaBoost. Such process, however, is very computationally...
Modern platform FPGAs integrate fine-grained reconfigurable logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodologies have not kept up with the rise in complexity of the target hardware. In particular, there is little overlap between the programming model for embedded software running on a real-time operating system and the programming...
Designers of FPGA-based systems are increasingly including soft processors-processors implemented in programmable logic-in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency as the best metric with which to compare potential designs. In this paper we demonstrate that 3, 5,...
The hthreads group is developing the hybridthreads compiler (HTC) to satisfy the need for a C compiler that can generate hardware threads. Compiling C-like languages to hardware has been studied a number of times. The goal of past projects is different than the goal of HTC because past projects focused on creating and optimizing hardware based co-processors that interleave execution of a single thread...
This paper describes a number of microarchitectural techniques for supporting multithreading in soft processor cores. These include a new thread scheduler that combines interleaved and block multithreading; a table of operation latencies (TOOL) for determining instruction latencies; support of arbitrary-latency custom computational units; and a multi-banked register file for supporting simultaneous...
WSAT and its variants are one of the best performing stochastic local search algorithms for the satisfiability (SAT) problem. In this paper, we propose an FPGA solver for very large SAT problems based on a WSAT algorithm. In our solver, parallel and multi-thread processing are combined (1) to fully utilize parallel accesses to external memory banks, and (2) to enhance the utilization of internal memory...
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