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Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full...
A high performance RLS lattice filter with evaluation of an unknown order of identified system was implemented as an accelerator PCORE for Xilinx EDK. The accelerator hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programing and debugging of a hardware accelerated DSP applications. The optimal logarithmic number...
QR decomposition, especially through the means of Householder transformation, is often used to solve least squares problems. A matrix to be decomposed with this method is usually very large, often large enough that it is not able to fit into the main memory of a workstation, let alone the internal memory of an FPGA nowadays. Efficient out-of-core algorithms have been developed to address the factorization...
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