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The uniqueness of human fingerprints has been accepted by the scientific community since long time ago. Proof of this is the fact that, among all physiological characteristics, fingerprints are the oldest and most deeply used signs of identity for personal recognition. However up to date, the development of an automatic fingerprint-based human authentication system is an open research problem. Most...
The aim of the hartes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hartes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW...
The paper presents the new hardware thread interface (HWTI), a meaningful and semantic rich target for a high level language to hardware descriptive language translator. The HWTI provides a hardware thread with the same thread system calls available to software threads, a fast global distributed memory, support for pointers, a generalized function call model including recursion, local variable declaration,...
Modern platform FPGAs integrate fine-grained reconfigurable logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodologies have not kept up with the rise in complexity of the target hardware. In particular, there is little overlap between the programming model for embedded software running on a real-time operating system and the programming...
In this paper, we investigate three different realizations of the same block from different points of view. The mentioned different realizations include two realizations with embedded processors (custom 16-bit RISC processor and general soft-core processor) and the third realization uses Handel-C as an example of synthesisable high-level abstraction languages. The results show that development time...
Tool path generation is one of the most complex problems in computer aided manufacturing. The algorithm called virtual digitizing avoids this problem by its own definition but its computing cost is high. Presented in the paper there is a virtual digitizing hardware/software architecture that takes advantage of field programmable gate arrays (FPGAs) to improve the algorithm efficiency and to meet the...
The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board...
We introduce a new execution model for orchestrating the interaction between the conventional processor and the re-configurable compute unit in adaptive computer systems. We then characterize the architectural and OS-level requirements of implementing the model, and demonstrate how they can be achieved on a real hardware platform running under a full scale multi-tasking virtual protected memory operating...
A formal methodology for automatic hardware-software partitioning and co-scheduling between the muP and the field programmable gate array (FPGA) has not yet been established. Current work in automatic task partitioning and scheduling for the reconfigurable systems strictly addresses the FPGA hardware, and does not take advantage of the synergy between the microprocessor and the FPGA. In this research,...
In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, available in the algorithms. Our designs are generated with a view of actual hardware/software co-execution on a real hardware platform. The carried experiments on the MOLEN polymorphic processor prototype suggest overall application...
Since the 1990s reusable functional blocks, well known as IP-Cores, have been integrated on one silicon die. These systems-on-chip (SoC) used a bus-based system for intermodule communication. Technology, performance and flexibility issues require the introduction of a novel communication system called network-on-chip (NoC). Around 1999 this method was introduced and since then has been investigated...
In this paper a new hardware-software co-design flow for FPGA based image processing systems is described. This flow is fully C++ based and allows specification, verification and semi-automatic generation of all necessary software and hardware components. It allows the involvement of algorithm developers in the majority of the design stages, without requiring hardware knowledge. The application is...
An important step in Heterogeneous System Development is Hardware/Software Partitioning. This process involves exploring a huge design space. By using profiling to select hot-spots and estimate area and delay we can prune the design space considerably. We present a Quantitative Model that makes early predictions to prune the design space and support the partitioning process. The model is based on...
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