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Modern FPGAs have become so affordable that they can be used to substitute ASICs in mass produced devices. A key component of such configurable system on a chip (CSoC) is the processor core. Available and usable cores are either 32 or 8 bit wide. Thus, there is a gap between these two extremes, which we want to fill with our SoC kit. In this contribution we elaborate on our SoC kit and its components...
Structured ASICs have emerged as a mid-way between cell-based ASICs with high NRE costs and FPGAs with high unit costs. Though the structured ASIC fabric attacks mask and other fixed cost it does not solve verification, particularly physical verification issues with ASICs or logic errors missed by simulation which would require re-spins. These can be avoided by testing in-system with an FPGA and migrating...
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and was designed to emulate a distributed-memory message-passing architecture. The system consists of 768-1008 MicroBlaze cores in 64-84 Virtex-II Pro 70 FPGAs on 16-21 BEE2 boards, surpassing the milestone of 1000 cores in a...
In this paper, we investigate three different realizations of the same block from different points of view. The mentioned different realizations include two realizations with embedded processors (custom 16-bit RISC processor and general soft-core processor) and the third realization uses Handel-C as an example of synthesisable high-level abstraction languages. The results show that development time...
Tool path generation is one of the most complex problems in computer aided manufacturing. The algorithm called virtual digitizing avoids this problem by its own definition but its computing cost is high. Presented in the paper there is a virtual digitizing hardware/software architecture that takes advantage of field programmable gate arrays (FPGAs) to improve the algorithm efficiency and to meet the...
Designers of FPGA-based systems are increasingly including soft processors-processors implemented in programmable logic-in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency as the best metric with which to compare potential designs. In this paper we demonstrate that 3, 5,...
A biological organism's ability to sense and adapt to its environment is essential to-its survival. Likewise, environmentally aware computing systems avail themselves to a longer operational life and a wider range of applications than traditional systems. In this paper, we propose a novel circuit design methodology that allows parameterizable hardware to self-regulate its temperature. We apply this...
The benchmark of pricing a European option via Monte Carlo simulation is commonly used in financial engineering for evaluating the performance of new computational techniques and to tune the parameters of the Monte Carlo simulation for improved convergence. This paper presents a comparison of different FPGA implementations of the European option benchmark against other implementations using GPUs,...
Modeling of physical phenomena often involves the use of complex sets of equations whose computational solution has demanding requirements in terms of memory and computing power. Finite-difference time-domain (FD-TD) method is a technique widely used nowadays in a variety of areas, such as antennas design, medical studies, circuit packaging and non destructive evaluation (NDE), having the advantage...
Modern FPGAs' parallel computing capability and their ability to be reconfigured make them an ideal platform to build accelerators for supercomputing systems. As a multi-core processor, the recently announced Cell Broadband EngineTMl offers tremendous computing power. In this paper, we introduce a prototype system that combines these two types of computing devices together in a reconfigurable blade...
A formal methodology for automatic hardware-software partitioning and co-scheduling between the muP and the field programmable gate array (FPGA) has not yet been established. Current work in automatic task partitioning and scheduling for the reconfigurable systems strictly addresses the FPGA hardware, and does not take advantage of the synergy between the microprocessor and the FPGA. In this research,...
A new scalable systolic hardware architecture for RSA cryptosystems is presented. The kernel of the architecture can operate with different precision of inputs which enables making area-time tradeoff in design. The add-shift Montgomery algorithm is used for modular multiplication. Unlike previous approaches after add operation, the result is shifted to the previous systole to divide by radix. This...
In this paper, we describe a hardware algorithm for the minimum p-quasi clique cover (MPQCC) problem and its implementation on an FPGA. MPQCC problem is a combinational optimization problem that is NP-complete. Furthermore, gene expression profile analysis is one of applied fields of MPQCC problem. We aim to develop an inexpensive acceleration system using FPGAs for gene expression profile analysis...
A novel routing fabric is introduced that offers high flexibility at significant lower silicon cost compared to routing fabrics currently incorporated in many field programmable gate array (FPGA) devices, IP cores, and IP-core wrappers. The novel fabric is entirely constructed from multiplexers and unidirectional point-to-point connections, controlled by configuration bits, and prove very efficient...
FPGA is currently a very important design technology to implement electronic systems due to its high logic density, its fast time-to-market and its low cost. But in order to provide high logic density FPGA devices are fabricated with nanometer CMOS technology that is becoming susceptible to radiation-induced soft errors. Among these errors, single-event transients (SETs) are those that are induced...
Multiple sequence alignment problems in computational biology have been focused recently because of the rapid growth of sequence databases. By computing alignment, we can understand similarity among the sequences. In this paper, we describe a compact system with an FPGA board and a host computer for multiple sequence alignment based on Carrillo-Lipman method. In our system, two dimensional dynamic...
Process variations of deep sub-micron technologies have created significant timing uncertainty. This generates the need for a new variability-aware physical synthesis tool for Field-Programmable Gate-Arrays (FPGAs). Ideally, variability-aware tools should be able to perform both timing variability estimation during the synthesis and timing variability analysis after the synthesis. Statistical static...
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