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A novel 3D computational self-consistent electro-thermal modeling methodology is developed to more precisely analyze leakage currents in nanoscale FinFET devices. The coupled electro-thermal modeling is applied to compare the device performance of poly-Si gate and metal-gate DG-FinFET. Results show very high leakage current in band-edge metal-gate device and poly-Si gate device. Mid-gap metal-gate...
In the past 10 years, CMOS technology scaling has continued at the rate of every 1 frac12 to 2 years per node. As CMOS technology advanced in to nano technology regime, static power or standby power increases at a much faster rate than dynamic power or active power, and it is expected to dominate the total device power dissipation. In this paper, we will review major leakage components that contributed...
Optimizing leakage currents in embedded memories is a major challenge, especially for portable applications. Increasing Vt of concerned memory transistors may not be the solution when target applications are also requiring high working frequencies. We describe in this paper a proven ROM architecture that reduces significantly leakage, without speed penalty. A dedicated testchip using a 0.18 mum CMOS...
MOSFETs with high-k gate stack (HfAlOx/SiO2) and those with SiO2 showed characteristic degradation induced by Ar-based electron cyclotron resonance (ECR) plasma, i.e., the increase in off-state leakage current (IOff). The measurements of all source-to-drain current paths in MOSFETs revealed that the leakage through S/D-body junction was dominant. For both cases of the high-k gate stack and SiO2, n-MOSFETs...
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