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This paper proposes debug patterns combined with an intuitive flow to accelerate and simplify the debugging of SystemC designs. A debug pattern provides a formalized procedure to fix a defect (also colloquial bug) that is notified by an always recurring failure symptom. It helps to focus the user's attention on a higher level of abstraction joined with minimal learning effort. The presented methodology...
In the work typical ESD failures of integrated circuits and ESD testing methods are presented. Authors describe dependencies between ESD models and different ESD failures. In order to allow more advanced ESD testing of integrated circuits, transmission line pulsing is proposed and its correlation to HBM method described. Finally conclusions based on up-to-date research and test results obtained with...
In this paper, a low-power high-speed CMOS full adder core is proposed for embedded system. Based on a new three-input exclusive OR (3-XOR) design, the new hybrid full adder is composed of pass-transistor logic and static CMOS logic. The main design objectives for the full adder core are providing not only low power and high speed but also with driving capability. Using TSMC CMOS 0.35-mum technology,...
Hardware accelerators for approximate string matching play an important role in an increasing number of modern bioinformatic applications. They are able to reduce the task complexity from quadratic to linear and show a speed up in orders of hundreds when compared with the respective software implementation. However, their wider use is limited by the lack of flexibility and modularity required by often...
Vower consumption has become increasingly more important with the advent mobile and wireless devices. This paper presents a clockless implementation of LEON2 processor IP core as a possible solution to the reduction of the processor power consumption. The de-synchronization methodology can be considered as a fast and efficient way to convert synchronous circuits into asynchronous ones. The design...
High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result in their own set of faults, and increase the complexity of already known faults. This paper describes the influence of bit line coupling on precharge faults, where the memory is rendered unable to set the proper precharge voltages...
The paper deals with the problems of logic function decomposition in Reed-Muller spectral domain. The Ashenhurst and the Curtis decompositions are considered. The decompositions are executed on positive polarization Reed-Muller spectrum of decomposed functions. The elaborated methods of decomposition are guided to implementation of logic functions in LUT based FPGA. The results are very promising.
Fast Fourier transform (FFT) computing may improved using two ways: the first way consist in packing two separate real functions into the complex input array in such a way that their individual transforms can be separated from the result; the second method used to improve the FFT computation consists in packing the real input of length N array cleverly, without extra zeros, into a complex array having...
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). To avoid the prohibitive storage requirements for failure bitmaps and the complex data structures inherent in most algorithms for offline repair analysis, existing heuristics for built-in...
This paper proposes a new approach for the optimization process of the interval addition and multiplication floating point units. For the interval addition/subtraction, an adder exploiting the parallelism of the double path adder structure is used. The two floating point additions needed are performed simultaneously on different data paths. Therefore, the performance of the proposed adder can be the...
The paper presents an efficient crosstalk simulator tool "XSIM" and it's methodology for analysis and modeling of signal integrity faults in deep sub-micron chips. The tool is used for analyzing the crosstalk coupling behavior in both defective and defect-free two parallel interconnects. Using the XSIM tool one can also determine the critical values of RLGC parasitics of interconnects and...
This paper presents an aggregation of simulated models for a wireless data acquisition system. The model consists of key units that were simulated using SIMULINK. The output signal from the transmitter was encoded to digital signal based on one of the pulse coding modulation (PCM) algorithms. At the receiver end, the signal is demodulated and processed to extract the spectrum of the original analogue...
Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip designs. Nevertheless, FPGA vendors can not accurately specify the energy consumption information of their products on the device data sheets because the energy consumption of FPGAs is strongly dependent on target circuit including resource utilization, logic partitioning,...
With the shrinking technology and increasing statistical defects, multiple design respins are required based on yield learning. Hence, a solution is required to efficiently diagnose the failure types of memory during production in the shortest time frame possible. This paper introduces a novel method of fault classification through image based prognosis of predefined fail signature dictionary. In...
A method for reliable measurement of interconnect delays is presented in the paper. The mode of test vectors generation never induces crosstalks. That is why the delay measurement is reliable. Also, minimization of ground bounce noises and reduction of power consumption during the test is an additional advantage. The presented method allows also localizing and identifying static faults of both stuck-at...
Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electronic circuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel designs of fault-tolerant flip-flops encompass multiple latches, which can also be used to accommodate the double-latched scan for dynamic test. The resulting scan-path elements are fault-tolerant...
The analysis and the measurement technique of the RF transformer model is presented. Transformer is used to improve the SNR of the input stages and for DC biasing through the winding inductance. The frequency range 0.1 MHz to 10 MHz utilized by the conventional ultrasound is assumed. Model is incorporating the winding resistances and the core loss resistance. The winding resistances experimental measurements...
A novel, patent pending, technique to design random bit generators, suitable to be integrated in a cryptographic device, is presented. The proposed generator is based on a high resolution phase noise detection in free running ring oscillators and it belongs to the class of stateless generators introduced by the authors in a previous work. Therefore, the quality (entropy per bit) of the produced bit...
The adoption of systems-on-chip (SoCs) in different types of applications represents an attracting solution. However, the high integration level of SoCs increases the sensitivity to transient faults and consequently introduces some reliability concerns. Several solutions have been proposed to attack this issue, mainly intended to face faults in the processor or in the memory. In this paper, we propose...
This paper describes a test data compression method based on pattern overlapping. We report here improvements that have been done on the test pattern compaction and compression algorithm called COMPAS. This algorithm reorders and compresses test patterns previously generated in an ATPG in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. It compresses...
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