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To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant...
The inter-die and intra-die variations in process parameters (in particular, threshold voltage (Vt)) can lead to large number of failures in an SRAM array, thereby, degrading the design yield in nanometer technologies. To improve parametric yield of nano-scaled memories, different circuit and architectural level techniques can be used. In this paper, we first analyze and model different SRAM failures...
Most of the early work on testing asynchronous combinational circuits ignored faults inside C elements, a common building block in these circuits. Using a standard cell based design, where C elements are built using majority gates, we show that a number of faults are untestable in some implementations, while others are undetected by previously proposed tests, which yield a fault coverage of only 70-80%...
Non-volatile embedded Flash (eFlash) memories are very popular in Systems-on-a-Chip (SoC). These memories are based on the well-known floating gate concept. While densities and quality constraints are increasing, the reliability becomes a growing up issue. For eFlash memories, endurance and retention issues are at the root of reliability losses. To improve reliability, eFlash memories designs usually...
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