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This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults. It will also protect the system against side-channel attacks, in particular fault-based attacks, i.e. the injection of faults in order to retrieve...
Memory is a significant performance limiting factor of the multiprocessor systems especially when shared. In FPGAs, the memory amount of the device is fixed and thus, optimal memory usage is essential. This paper analyses how the fixed amount of memory should be divided between instruction memories and instruction caches for multiprocessor systems and compromised with the number of processors. The...
The aim of this paper is to present a simple, lightweight, multi-threaded network processor core implemented in a FPGA circuit 1. The authors prove that it is possible to design a processor core with hardware switched threads in a FPGA integrated circuit efficiently. The details of the processor core's architecture are described. The compilation results prove, that the proposed core is able to run...
Vower consumption has become increasingly more important with the advent mobile and wireless devices. This paper presents a clockless implementation of LEON2 processor IP core as a possible solution to the reduction of the processor power consumption. The de-synchronization methodology can be considered as a fast and efficient way to convert synchronous circuits into asynchronous ones. The design...
This paper proposes a new approach for the optimization process of the interval addition and multiplication floating point units. For the interval addition/subtraction, an adder exploiting the parallelism of the double path adder structure is used. The two floating point additions needed are performed simultaneously on different data paths. Therefore, the performance of the proposed adder can be the...
The paper presents an efficient crosstalk simulator tool "XSIM" and it's methodology for analysis and modeling of signal integrity faults in deep sub-micron chips. The tool is used for analyzing the crosstalk coupling behavior in both defective and defect-free two parallel interconnects. Using the XSIM tool one can also determine the critical values of RLGC parasitics of interconnects and...
The adoption of systems-on-chip (SoCs) in different types of applications represents an attracting solution. However, the high integration level of SoCs increases the sensitivity to transient faults and consequently introduces some reliability concerns. Several solutions have been proposed to attack this issue, mainly intended to face faults in the processor or in the memory. In this paper, we propose...
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