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To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant...
In this work a co-synthesis method, which allows for optimization of dynamically self-reconfigurable SOPC system architecture, is presented. Partially reconfigurable FPGAs let better use hardware resources due to reuse of the same parts of the chip for different functionalities in the same application. The algorithm maximizes speed of the SOPC system taking into consideration FPGA's area constraints...
Highly parallel architecture for local histogram equalisation is studied. Three different kinds of approaches to the parallel architecture are regarded in this paper. (1) Module-level -which focuses on processing as many data as possible within a single module. (2) 1D -Several modules conducting simultaneously histogram equalization on partially overlapping (either horizontally or vertically) frames...
Modern FPLD devices have a very complex structure. They combine PLA-like structures as well as FPGA's and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLD's to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation...
Memory is a significant performance limiting factor of the multiprocessor systems especially when shared. In FPGAs, the memory amount of the device is fixed and thus, optimal memory usage is essential. This paper analyses how the fixed amount of memory should be divided between instruction memories and instruction caches for multiprocessor systems and compromised with the number of processors. The...
The aim of this paper is to present a simple, lightweight, multi-threaded network processor core implemented in a FPGA circuit 1. The authors prove that it is possible to design a processor core with hardware switched threads in a FPGA integrated circuit efficiently. The details of the processor core's architecture are described. The compilation results prove, that the proposed core is able to run...
The paper deals with the problems of logic function decomposition in Reed-Muller spectral domain. The Ashenhurst and the Curtis decompositions are considered. The decompositions are executed on positive polarization Reed-Muller spectrum of decomposed functions. The elaborated methods of decomposition are guided to implementation of logic functions in LUT based FPGA. The results are very promising.
Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip designs. Nevertheless, FPGA vendors can not accurately specify the energy consumption information of their products on the device data sheets because the energy consumption of FPGAs is strongly dependent on target circuit including resource utilization, logic partitioning,...
Reconfigurable computing has grown to become important in hardware design. In autumn 2005, we taught for the first time a new course in digital system design with its main focus on FPGA technology and design using VHDL. This paper reports about the various issues dealt with including what topics to cover, text book selection, lab exercises etc. A summary of the students feedback is also included.
The paper examines the feasibility of using neural network based image compression in the implementation on single FPGA based platforms. There are examined two paradigms of neural networks in the paper -multilayer perceptron as supervised learning representative, and self-organizing feature map as unsupervised learning or self-organization representative.
The utilization of FPGA in supercomputing is an emerging idea. That is obviously due to the progress in semiconductor technology. Today's FPGA capacity allow for double precision floating point arithmetic implementation. In this paper authors present their approach to the custom matrix multiplication implementation. Matrix multiplication is a key operation in linear algebra scientific calculations...
Compression of digital audio signals has become very important audio computation process. When audio data are compressed it is possible to store more data in a smaller memory and to increase the overall audio data throughput transferred through an interface. Several compression schemes were developed and well established. Most of them adopt the MDCT/IMDCT. This paper presents an software tool, an...
Network intrusion detection systems (IDS) are becoming an important tool for securing critical information and infrastructure. Current software-based IDS often fails to keep up with high-speed network links so a hardware based IDS is requested. This paper deals with design and implementation of complete hardware accelerated IDS solution based on field-programmable gate array (FPGA). Core generator...
The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for duplex system design, each including the combination of totally self-checking blocks based on parity predictors to obtain better dependability parameters. Combinatorial circuit benchmarks have been considered in all our experiments...
From an assumed property, which constrains the inputs of a design under test, we produce a RTL synthesizable design that generates compliant sequences of values for all the signals named in the property. Such generator can be connected to the design under test for verification by simulation or emulation. Experiments on our prototype tool show that the technique is efficient, and allows to test the...
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