The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Reduction in power consumption has been an important concern in low-power and high-performance systems. This paper addresses the problem of static voltage scaling in such systems which is a well studied technique. In this paper we present an optimal methodology for static voltage scaling. Previous techniques use path-based timing constraints in the system model which requires exponential runtime even...
In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amplify the effect of inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of...
An important factor which greatly affects the power consumption and the delay of a circuit is the input capacitance of its gates. High input capacitances increase the power consumption as well as the time for charging and discharging the inputs. Current approaches address this problem either through gate-level only resynthesis and optimization, or indirectly through transistor-level synthesis aimed...
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation of both dynamic and leakage power, including the power dissipation due to emerging leakage mechanisms such as gate oxide tunneling, for partitioned arrays that deploy data-retaining sleep techniques for leakage reduction....
This paper presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in fading channels. The proposed scheme pre-analyzes each received data frame to estimate the maximum number of necessary iterations for the frame convergence. The results are then used to dynamically adjust decoder frequency and switch between multiple-voltage...
In the past, dynamic voltage and frequency scaling (DVFS) has been widely used for power and energy optimization in embedded system design. As thermal issues become increasingly prominent, we propose design-time thermal optimization techniques for embedded systems. By carefully planning DVFS at design time, our techniques proactively optimize system thermal profile, prevent run-time thermal emergencies,...
Circuit timing and power analysis are important in various aspects of circuit optimization. In order to solve the problem of finding input vectors to activate worst-case timing or power, a concept called timed characteristic function (TCF) was proposed, which can characterize logical and temporal conditions simultaneously. Traditionally TCF assumes the (one-vector) floating mode of operation. In this...
It is well known that leakage savings using transistor stacks is not effective in double-gate technologies such as FinFETs (back and front-gate connected together), due to the absence of body effect. However, transistor stacking along with independent gate operation of FinFETs can offer larger leakage savings compared to that of bulk devices. In this paper, we show that the sleep transistor based...
Voltage island has become a very effective design style for power saving by assigning different supply voltages to different modules. However, the new design style also brings forward new challenges, especially to the designer of P/G networks. In this paper, we study the power delivery problem in voltage island designs, and propose to consider voltage drop during the floorplanning process to reduce...
A methodology based on supply voltage scaling for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock signal is distributed globally at a lower optimum supply voltage. To maintain the speed of the system, a dual supply voltage (dual-VDD) clock distribution network is presented. Level converters are utilized to...
Energy efficient computing is a first order design concern in portable devices. This paper describes a design approach that enables operation of a processor in various performance-energy modes. Depending on the workload and performance requirements, the processor can easily switch between these modes and save energy while still computing jobs in the required time. The proposed approach can also be...
We propose a new bandgap reference topology for supply voltages as low as one diode drop (~0.8V). In conventional low-voltage references, supply voltage is limited by the generated reference voltage. Also, the proposed topology generates the reference voltage at the output of the feedback amplifier. This eliminates the need for an additional output buffer, otherwise required in conventional topologies...
This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3 GPP WCDMA modem
This paper describes an 8-bit, 10 MSamples/second analog to digital converter, with 2V fully differential input range, which is implemented in TSMC 0.25mum CMOS technology. It achieves low power dissipation of 25mW, and the chip area is 0.56mm2. Measured performance yields a very good VTC curve and a sine wave fitting curve for 200KHz input at 10Msample/s, DNL testing of -0.2LSB-0.75LSB; INL testing...
Multi-threshold voltage CMOS (MTCMOS) has emerged as an increasingly popular technique for reducing the leakage energy consumption of idle circuits. The MTCMOS circuits, however, suffer from high energy overhead during the transitions between the active and standby modes. A new circuit technique is proposed in this paper to lower the energy overhead of these mode transitions for effective energy reduction...
As VLSI technologies scale into the deep submicron (DSM) realm, the minimum feature size continues to shrink. In contrast, the average die size is expected to remain constant or to slightly increase with each technology generation. This results in an average increase in the global interconnect lengths. In order to mitigate the impact of these global wires, buffer insertion is the most widely used...
The following topics are dealt with: quality electronic design; design for manufacturing; device and circuit reliability; power and thermal management; analog and mixed signal design; circuit quality and reliability; advances in timing and power in physical design; power-aware system design methodologies; electrical quality; analog and RF testing; low power circuits; package circuit co-design; high...
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream technique to exploit the tradeoff. Physical design, specifically repeater insertion and sizing, is naturally signed-off at the highest performance mode. We observe that through simple modifications to the repeaters (buffers and...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.