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A systematic study to optimize gate stack constituents (interface, high- K, metal gate) to maximize carrier mobility with aggressively scaled equivalent oxide thickness (EOT) is presented. We identify ultra-thin thermal oxide, atomic layer deposited HfSiON and optimized plasma nitridation performed in sequence as the optimized run path for sub-nm EOT scaling with high carrier mobility. A metal gate...
The following topics are dealt with: high performance MOSFET; electron transport and noise; advance gate stack; MEMS; microsensors; novel gate-stack CMOS solutions; advanced nanoscale device transport models; RF passive integration; carbon nanotubes; memory circuits; NVM high-K dielectrics; high voltage devices; injection devices; transport devices; imagers; light emitting devices; process integration;...
We report on the fabrication and measurement of triangular gate-all-around (GAA) and tri-gate devices. On the small triangular cross-section devices we observe a significant enhancement of the extracted carrier mobility (up to ~1000cm2/Vs). We assign this effect to enhanced conduction in the sharp corners of our device, and local volume inversion. The new concept of local volume inversion is supported...
This paper reports the effect of shallow-trench-isolation (STI) on generation-recombination (G-R) noise and flicker noise variation in 0.13-μm RF MOSFETs for the first time. The devices with relatively small finger widths (W = 1 μm/Nfinger = 40 and W= 5 μm/Nfinger = 8) presented more pronounced G-R noise compared to those with W= 10 mum/Nfinger = 4 devices. In addition, a wide variation of noise levels...
This paper have investigated the threshold voltage dispersion and the impurity scattering limited mobility in carbon nanotube field effect transistors with randomly doped source and drain extensions. Accurate transport simulations have been performed solving the self-consistent 3D Poisson-Schrodinger equation, within the non-equilibrium Green's function formalism. In particular, non-ballistic transport...
In this paper, two Monte-Carlo simulators implementing different models of the influence of carrier quantization on the electrostatics and transport are applied to sub-100nm double-gate SOI devices. To this purpose a new stable and efficient scheme to implement the contacts in the simulation of DG SOI devices is introduced first. Then, results in terms of drain current and microscopic quantities are...
The low field mobility in double- and single-gate structures is analyzed for (100) and (110) SOI substrate orientation. Due to volume inversion, mobility in double-gate ultra-thin body (110) SOI FETs is enhanced in comparison with the mobility of single-gate structures in the whole effective field range. In double-gate (100) structures the mobility decreases below the single-gate value for high effective...
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