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The adoption of SOI structure into 90 nm IC devices makes the characterization very challenging. TEM characterization becomes more critical, challenging and indispensable in the failure analysis of such devices. To illustrate the application of TEM in this area, several unique examples including both cross-sectional and planar analysis are given here
Failure analysis (FA) is key in root cause identification for any problem solving journey. Diagnosis given provides insights on mechanisms by which failures occur. This helps in determining factors that lead to the failure and consequently the root cause, thus easier to provide corrective actions. In mid June 2004, a sudden increase in test fall-outs was encountered. Several devices from different...
Electromigration and stress migration lifetimes are characterized as a function of metal thickness for Cu interconnects fabricated using 0.13 mum process technology. The stress migration lifetime decreases as metal thickness decreases, consistent with previous studies. The electromigration lifetime shows a more complicated dependence on metal thickness. For vias landing on narrow lines, the electromigration...
This paper describes a new dc-coupled laser induced detection system for fault localization in microelectronic failure analysis. This method removes artifacts inherent in ac-coupled detection systems and is capable of producing an accurate mapping of the laser induced resistance change of the devices without signal attenuation. This method is also capable of localizing large area faults without signal...
Optical techniques (light emission and laser stimulation techniques) are routinely used for precise IC defect localization. At the early stage of an analysis, choosing the right technique is an increasingly complex task. In some cases, one technique may bring value but no the others. Using an 180nm test structure device we present results showing the complementary of emission microscopy (EMMI), time-resolved...
Thermal (TLS) and photoelectric (PLS) laser stimulation techniques are now widely used in failure analysis of integrated circuits. The stimulation signatures when using a 1064 nm laser are often a combination of PLS and TLS. This work presents a quantitative investigation of 1064 nm laser stimulation effects on single NMOSFET devices that isolates the two contributors. The results support the basic...
The purpose of this paper is to present a novel deductive methodology, which is accomplished by applying difference analysis to nano-probing technique. This methodology would like to resolve the erratic device with a tailing failure or puzzling feature, but not only to check if the suspect had incorrect characteristic or mismatched transistor parameters
In this paper, systematic pair bit failure is analyzed in failure bit map of deep-submicron CMOS technology. Tungsten plug corrosion in contacts of stacked contact/metal/via structure is observed from careful analysis of failure bit. Then, some experiments have been carried out to identify and resolve this corrosion failure. This corrosion reaction occurred through the void space, which is formed...
Companies estimate the NBTI lifetime of SRAM memories usually by extrapolation of the DC degradation. This method underestimates the lifetime of the memory cell since the bit change in the cell over time is neglected. In this work we have analyzed the impact of storing random bit values in a 6T-SRAM memory cell by using probabilities of storing a one bit between the boundaries of 100% (fully unsymmetric...
Using a circular beam separator to deflect the primary beam of an SEM through 90deg, an aberration limited final probe size of 7-8 nm has been achieved in experiments. This limit was shown to be due to magnetic leakage fields from the post-deflector lens and not due to aberrations of the beam separator. In fact, it is concluded that the beam separator aberrations are within 2 nm over a 1 mum by 1...
In this paper, experimental features of a non-classical hot-electron gate current Ige obtained under Vb = 0, similar to those reported earlier under reverse Vb are presented. To the best of our knowledge, this is the first direct observation of this non-classical Ige component in deep submicrometer N-channel MOSFET under conventional CHE biasing, i.e. when Vg ap Vd and Vb = 0. Based on the results,...
The combined use of scanning probe microscope based techniques, namely conductive atomic force microscopy (C-AFM) and tunneling atomic force microscopy (TUNA), and nanoprobing technique is presented. In 90 nm process and below, C-AFM identifies leakage by current mapping, while TUNA measures the current-voltage (I-V) curves of different contacts to study the integrity of individual contacts. Nanoprobing...
Surface charging is encountered in the study Auger electron spectroscopy of non-conducting surfaces. In this paper, two case studies of (i) Au-pad of packaged die unit and (ii) floating Al-pads of patterned wafer were presented. Surface charging was noticed in both the samples and it was not possible to eliminate the effect with convention charge reduction methods. Two FIB-based methods of charge...
In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1 nm (EOT). With the scaling of gate oxide thickness into 1 nm regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method...
The importance of understanding asymmetrical behaviour in SRAM has increased as the technology node shrinks below 100 nm. Single bit failure can possibly be caused by the malfunction of any of the six transistors in a standard SRAM cell. In order to understand the asymmetrical behaviour in advanced nano SRAM devices, nanoprobing is introduced to perform transistor level fault isolation prior to attempting...
The effect of gate-oxide reliability in MOSFET on common-source amplifiers is investigated with the non-stacked and stacked structures in a 130-nm low-voltage CMOS process. The supply voltage of 2.5 V is applied on the amplifiers to accelerate and observe the impact of gate-oxide reliability on circuit performances including small-signal gain, unity-gain frequency, and output DC voltage level under...
The paper could limit itself to repeat the complaint that originated the first "Rules of the Rue Morgue", maybe updating the scenario of the many end users currently exposed to the risk of failed failure analyses. Nevertheless, some constructive proposals will be also pointed out, as those exposed by a recent paper (Cassanelli et al., 2005) that, dealing with the challenges in system reliability...
In this study, a wafer level chip scaled packaging (WLCSP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the fan-out WLCSP, the solder bumps could be located on both the filler polymer and chip surface. The concept of the fan-out WLCSP and the processes of fabricating the novel fan-out...
In the late years, many countries will begin to prohibit using the lead-based solders in microelectronic packaging processes in view of inherent toxicity of lead-based solder alloys. The waste electrical and electronic equipment (WEEE) directive by EU has claimed that the use of Pb in consumer electronics will be banned after January 2006. Therefore, the development of lead-free solders replacing...
In this paper, we demonstrate a practical alternative to the conventional SIL, which overcomes the above limitations. We show that it is possible to fabricate a lens directly on the back side of the silicon of the device under test. This lens works on principles of diffractive optics and is around 250 nm thick. The lens may be fabricated in about 1 hour, using a combination of FIB ion implantation...
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