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Negative bias temperature instability (NBTI) of p-MOSFETs gets recovered immediately when the stress is removed, and hence the electrical measurement will tend to underestimate the NBTI degradation due to its unavoidable measurement time. This measurement-induced additional NBTI recovery must also be taken into account, especially during the NBTI recovery process, because it directly affects the time...
Electrical and SEM analysis of gate-silicided (GS) and gate-non-silicided (GNS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism switches away from classical drain-to-source filamentation when the silicidation between the silicide-blocked drain/source and the polysilicon gate is avoided. For 2.5V thick oxide devices, drain-to-substrate junction shorting was observed, whereas,...
In this paper, we demonstrate for the first time via technology computer aided design (TCAD), the enhancement in both the ac and dc performances for process-induced strained-Si MOSFETs over bulk-Si and a comparison of process-induced strained and substrate-induced strained-Si MOSFETs. In addition, we present the hot-electron degradation characteristics for strained-Si n-MOSFETs fabricated in both...
This paper presents reliability investigations in NLDEMOS transistor in 0.13μm SOI CMOS technology. Reliability tests under hot carrier injections (HCI) for different gate-lengths show two different degradation mechanisms. The modification of current path with short overlap (Olap) due to oblique equi-potential lines and the increase in the vertical electrical field under the gate edge at low V g lead...
Thermal (TLS) and photoelectric (PLS) laser stimulation techniques are now widely used in failure analysis of integrated circuits. The stimulation signatures when using a 1064 nm laser are often a combination of PLS and TLS. This work presents a quantitative investigation of 1064 nm laser stimulation effects on single NMOSFET devices that isolates the two contributors. The results support the basic...
In this paper, experimental features of a non-classical hot-electron gate current Ige obtained under Vb = 0, similar to those reported earlier under reverse Vb are presented. To the best of our knowledge, this is the first direct observation of this non-classical Ige component in deep submicrometer N-channel MOSFET under conventional CHE biasing, i.e. when Vg ap Vd and Vb = 0. Based on the results,...
In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1 nm (EOT). With the scaling of gate oxide thickness into 1 nm regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method...
The effect of gate-oxide reliability in MOSFET on common-source amplifiers is investigated with the non-stacked and stacked structures in a 130-nm low-voltage CMOS process. The supply voltage of 2.5 V is applied on the amplifiers to accelerate and observe the impact of gate-oxide reliability on circuit performances including small-signal gain, unity-gain frequency, and output DC voltage level under...
Single-crystalline SGOI substrate is achieved by multi-step oxidation of co-sputtered amorphous SiGe film on SOI substrate. Subsequently, SGOI PMOSFET using Pt-germanosilicide Schottky S/D and HfO 2/TaN gate stack integrated with conventional self-aligned top gate process was demonstrated. Excellent performance of the SGOI PMOSFET is presented
In this work, the investigation of block oxide used in planar MOSFETs has been studied. To solve these above issues and for the comparison, we propose two novel device architectures; one is called the FDSOI with block oxide (bFDSOI) and the other is called the Si on partial insulator with block oxide field-effect transistor (bSPIFET)
In this study, we propose a LSC technique that using SiN capping layer deposition with high mechanical stress on single poly-Si gate. In addition, nMOSFETs with thicker poly-Si gate (220 nm) can also increase tensile strain in the channel region compared to that of the thinner (150nm) poly-Si gate structure. Furthermore, size dependence of nMOSFETs with SiN capping layer is also studied and compared...
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