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In this paper we report on experimentally obtained enhancement of hole mobility and sheet carrier density in Ge QW modulation doped (MOD) SiGe heterostructure via implementation of symmetric double-sides modulation doping
In this work, we revised fabrication process parameters (e.g., Ge fraction and growth temperature) and performed electrical measurements for high quality RTD with improved crystallinity. As a result, we could investigate relationships between structural parameters and hole tunneling properties in the fabricated RTDs
In this paper, the key design device parameter of SOI such as the buried oxide thickness, lateral scaling, and thermal effect are studied by 2D device simulator DESSIStrade
Summary form only given. The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits and the performance of optical...
We propose in this paper a detailed study of the growth kinetics of Si and SiGe in reduced pressure chemical vapor deposition on Si(100), Si(110) and Si(111) substrates. The gaseous chemistry used, dichlorosilane (SiH2Cl2) + germane (GeH4) + hydrochloric acid (HCl), is selective versus SiO2 and Si3N4. One should thus greatly benefit from such data when growing selectively either recessed SiGe sources...
Through 1D device simulations it has been shown that there is some advantage to engineering the shape of the collector profile in SiGe HBT's but only in certain regimes. Power law profiles are shown to be superior to a flat profile only for low breakdown cases. For high-breakdown devices there is little or no advantage to shaping the profile. For the low breakdown case, profiles with their dose distributed...
This work discusses the influence of the underlying SiGe on the growth kinetics during the deposition of the Si-cap layer. The importance and feasibility of the required process control is demonstrated by charge pumping measurements and energy dispersive X-ray spectroscopy (EDX) on pMOS devices. The analysis clearly demonstrates the influence of the Si thickness on the quality of the gate dielectric/channel...
The raw performance of normal incidence Ge on Si detectors has been found to be close to that of GaAs devices in optical properties at 850nm. In addition the leakage current is nearing that needed for many applications. Further receiver data that quantifies this is presented at the talk
We report about a top-side illuminated Ge photodetector, which is appropriate for transmission of high-speed data at infrared telecommunication wavelengths and is monolithically integrated on a standard Si substrate (Jutzi et al., 2005) for 1552 nm operation. A 3-dB-bandwidth of 38.9 GHz is achieved for a 10 mum diameter detector and a reverse bias of 2 V. These results demonstrate the potential of...
The requirements of Si-based photonic devices in the next generation of chip technologies have caused extensive studies on Ge/Si quantum dot devices. In this communication, we report on lateral three-terminal FET type of photodetectors based on Ge dot layers sandwiched between SiGe QWs, where the near-infrared light was mainly absorbed in the Ge island layers. In addition to the source and drain contacts,...
We report on ambipolar GeOI FETs fabricated on ultra-thin films of single crystal Ge, epitaxially grown on a high-k crystalline lanthanum-yttrium-oxide lattice matched to Si (111) substrate. The GeOI FETs show promising transistor characteristics at room temperature, while at low temperatures they exhibit negative differential resistance (NDR) in the drain current circuit
We have demonstrated the growth of strain-relaxed Ge1-xSnx buffer layers using virtual Ge(001) substrates. PDA effectively promoted the relaxation of the Ge1-x Snx layer, concomitantly with the lateral propagation of preexisting threading dislocations leaving misfit segments at the Ge 1-xSnx/Ge interface. Present results open up a scheme of fabricating strained channels which realize much high performance...
In modern RF BJTs and HBTs the collector is usually designed as selectively implanted collector (SIC). Therefore in the present work we investigate the influence of various SIC profiles on ft and f max with respect to BVCEO for four basic types of Si-based bipolar transistors: A SiGe HBT with a graded Ge content in the base, and second SiGe HBT having a much higher Ge content in the entire base, thus...
Introduction of C into Si1-xGex heteroepitaxial growth on Si has attracted considerable attention for fabrication of novel heterostructure devices in Si-based technology for the band engineering by strain control in group IV semiconductors (Eberl et al, 1992, Chang et al, 1998). In the previous work, carbon effect on strain compensation in Si1-x-yGexCy films epitaxially grown on Si(100) at 500 degC...
In this work, we have fabricated 8-inch SiGe wafers with the dual channel through a direct production line and the samples were mostly characterized by the line equipment. Some characteristic methods and vital specification were presented for device makers
In this paper, the origin of p-n junction leakage current in s-Si/SGOI diodes is investigated. It is found that generation current by bulk trap is dominant in the s-Si/SGOI p-n junction leakage current compared to diffusion current and generation current by oxide interface state and that the calculated leakage current is low enough even in Ge-on-insulator (GOI) channels at hp45 nm technology node
Here, a systematic study is made of the leakage current in huge-area SiGe-Si p+-n junctions. As will be shown, both the perimeter and area leakage current density are a sensitive function of the S/D etch depth, whereby a higher leakage is obtained for deeper trenches. This can be explained by the presence of dislocations at the SiGe-Si interface, as revealed by transmission electron microscopy (TEM)...
The aim of the present study was to complete a systematic investigation of metal-germanium reactions to isolate promising candidates for contacting Ge-based microelectronic devices. Based on their low formation temperature, low resistivity, limited film roughness, sufficient morphological stability, and limited sensitivity to oxidation, NiGe and PdGe were found to be the most promising candidates...
The SiGe SD structure in peripheral PMOS area of DRAM was successfully integrated without any degradation of peripheral NMOS properties, which is the first approach to DRAM. The PMOS performance enhancement was found to be more than 40%. The authors suggest the SiGe SD structure as the key solution for the improvement of peripheral PMOS transistor properties in sub-50nm DRAM technology
We developed a new bulk strained-Si/SiGe CMOS technology free from any Ge-related problems, which has a 90-110-nm strained-Si layer thicker than the limit at which misfit-dislocations occur, and a new shallow-trench isolation structure that has a selective-epitaxial Si layer to cover up the SiGe trench surface. This process has advantages in manufacturing compatibility with Si-CMOS process, low junction...
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