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Quantum dots in silicon/silicon-germanium offer several potential advantages for quantum computing, including long spin coherence times and compatibility with silicon device fabrication. Recently, it has become possible to use Schottky gates to define quantum dots in Si/SiGe heterostructures at low temperatures. Here we describe progress in the fabrication and measurement of silicon quantum dots,...
Our experiments demonstrate that Schottky-barrier reducing mechanisms can be overcome by adequately designed Si/SiGe heterostructures and that single electron transistor (SET) functionality can be achieved in modulation-doped Si/SiGe heterostructures with a standard split-gate approach that can easily be integrated into an array of coupled SETs
By using the low thermal conductivity of SiGe to increase the average temperature along the pn-junction of the structure, the efficiency and power output of our thermoelectric elements can be increased dramatically. Further improvement can be achieved by using optimized graded Ge content to fully adapt the temperature distribution to our needs
Electronics built on flexible polymer substrates have great potential for a number of applications. The largest potential lies in active-matrix flat-panel display applications, because of the continually increasing demand for light weight and robustness from wireless technologies. For the back-plane circuitry of active-matrix organic light emitting diodes (AMOLEDs), high transconductance (gm ) and...
We have developed a model of the time dependence of asymmetric strain generation in Si/SiGe bilayers on compliant substrates, and established a process window for maximum strain asymmetry. The resulting uniaxial silicon strain of 0.75% tension is well-controlled and uniform across the SOI islands
We have investigated strain relaxation of patterned SiGe lines after He implantation and annealing. Asymmetric relaxation of the SiGe lines transforms biaxial stress into nearly uniaxial stress for very narrow lines. The effect of the anisotropic stress on the carrier mobility of strained silicon on top of the SiGe lines will be discussed in the frame of the piezoelectric resistivity model as presented...
The demonstration of a semiconductor laser based on intersubband transitions in an InGaAs/InP cascade structure, has stimulated studies to transfer this approach to Si/SiGe. The feature, that intersubband transitions are by nature direct, made it appealing to use this concept to create a laser in a material with an indirect bandgap like Si. A laser in Si would allow the monolithic integration of optical...
Both the simulation and experimental results confirm that there exist upper and lower limits of carrier concentration in the quantum well. The small difference between the upper and lower limits explains the narrow distribution of 2DEG density from all published experimental observations in strained Si. We report the lowest as-grown carrier density to date in Si/SiGe heterostructures
Strained SOI-MOSFETs are promising device structures for high-performance CMOS applications, because of their high current drive and low parasitic capacitances. It has been demonstrated that uniform 150 and 200mm strained-Si/SGOI (SiGe-on-insulator) wafers with the ULSI grade have been successfully fabricated by the Ge condensation process to realize excellent device performances even for 35nm-gate-length...
In this paper, the first experiment results from Si/SiGe bound-to-continuum quantum cascade emitters are presented operating at THz frequencies. The quantum cascade emitters are grown by chemical vapour deposition (CVD)/gas source molecular beam epitaxy (MBE) and solid-source MBE
This work discusses the influence of the underlying SiGe on the growth kinetics during the deposition of the Si-cap layer. The importance and feasibility of the required process control is demonstrated by charge pumping measurements and energy dispersive X-ray spectroscopy (EDX) on pMOS devices. The analysis clearly demonstrates the influence of the Si thickness on the quality of the gate dielectric/channel...
In this work, we have fabricated 8-inch SiGe wafers with the dual channel through a direct production line and the samples were mostly characterized by the line equipment. Some characteristic methods and vital specification were presented for device makers
We developed a new bulk strained-Si/SiGe CMOS technology free from any Ge-related problems, which has a 90-110-nm strained-Si layer thicker than the limit at which misfit-dislocations occur, and a new shallow-trench isolation structure that has a selective-epitaxial Si layer to cover up the SiGe trench surface. This process has advantages in manufacturing compatibility with Si-CMOS process, low junction...
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