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Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both NMOS and PMOS performance to retain the same n:p ratio is desirable. Interactions between biaxial lattice strain, uniaxial relaxation, process-induced...
SiGe on insulator (SGOI) is a typical template substrate for strained Si-on-insulator (SOI) structures, which can enjoy both benefits of the mobility enhancement by strained channels and the low junction capacitance by SOI structures. In order to fabricate the high performance MOSFET, formation of the highly strained Si layers on SGOI without dislocations and defects is quite important. This means...
Among the new architectures that are under development for the very advanced technological nodes, the SON transistors are very promising, insofar as they allow a better electrostatic control of the conduction, compared with standard MOSFETs. The consequence is a limited power loss, which is desirable for mobile devices applications. Several publications from Monfray et al. describe the SON concept...
In this work, we report the demonstration of a novel CMOS process with substrate-strained-SiGe pMOSFET and mechanical-strained Si nMOSFET fabricated on one chip. The device structure combines the advantages of compressively SiGe materials and tensile Si induced by SiN layer to achieve higher carrier mobility. Moreover, due to the separation process of two kind devices, individual MOSFETs was tuned...
In this paper, we report the width dependence of short channel effect in strained-Si nMOSFETs. The trade-off between electron mobility enhancement and SCE control for various Ge contents and Si-cap layer thicknesses in the relaxed SiGe buffer are demonstrated. Finally, our work presents the optimum processes window for strained-Si device in advanced CMOS technology
The scaling of some today's high mobility MOSFETs solutions was discussed. The enhancement (between 10-25% for sub-40nm devices) is often lower than the natural mobility decrease due to high short-channel doping (for bulk) or border S/D effects (on SOI). Further understanding of the short channel scattering effects is necessary to engineer next generation high mobility channels
To lower C content can keep performance enhancement of strained-Si:C devices since it minimizes the alloy scattering potential, interstitial trap and Dit. The large Dit at oxide/strained-Si:C interface degrades the expected carrier mobility enhancement, but improvement is observed after forming gas annealing. The strained-Si:C channel makes it possible to have high speed devices, improved short channel...
Germanium-carbon alloys (Ge1-xCx) were first deposited on Si (100) by chemical vapor deposition using precursors containing Ge-C bonds. The stated objective of that work was to explore Ge1-xCx as a potentially lattice-matched system with Si capable of bandgap engineering. In step with renewed interest in Ge MOSFET devices due to the advent of high-kappa dielectrics, our group has revisited Ge1-xCx...
In this paper, fabrication of the dual channel CMOS devices based on the Ge-condensation technique is demonstrated as well as their mobility and current drive enhancements. Ge-rich strained SGOI pMOSFETs were integrated with strained Si/SGOI nMOSFETs by a CMOS process combined with the Ge condensation process, in which the strain in the SGOI layers were properly controlled. As a result, significant...
In this talk, the authors first review the earlier results on high-mobility, biaxially strained Si, SiGe, and Ge channels grown on relaxed Si1-xGex/Si(001) buffers. Next, they discuss their experiments with SiGe growth on Si(110) and (111), with a particular emphasis on the unique dislocation morphologies that emerge. The author will also show that the growth kinetics and dislocation behavior on (110)...
This paper presents results on conventional, deep sub-micron short-channel Ge p-and nFET devices with a HiK/MG gate stack and NiGe source/drain regions. It is shown that the mobility enhancement observed in long channel Ge pFETs as compared to Si pFETs, can indeed result in deep sub-micron Ge devices with a higher drive
Strain engineering using lattice-mismatched S/D in transistors and their combination with other stressors and optimum surface/channel orientations is very attractive and important for the continued improvement of CMOS performance in addition to device scaling
This work investigates NMOSFETs on thick biaxially strained silicon for digital logic applications. Strain and long channel mobility enhancement are shown to be maintained for strained films as thick as 300 nm, 15 times thicker than the equilibrium critical thickness, and misfit-dislocation induced off-current leakage is shown to be completely eliminated for tSi equiv 100 nm. Significant performance...
Strained SOI-MOSFETs are promising device structures for high-performance CMOS applications, because of their high current drive and low parasitic capacitances. It has been demonstrated that uniform 150 and 200mm strained-Si/SGOI (SiGe-on-insulator) wafers with the ULSI grade have been successfully fabricated by the Ge condensation process to realize excellent device performances even for 35nm-gate-length...
In this work, the impact of high temperature annealing typical of CMOS processing on the surface morphology of thin SiGe SRBs is investigated for strained silicon layers above and below the critical thickness
In this paper, the optimum STI process and Ni silicide has proposed to realize the strained-Si nMOSFET. Device sizes dependence of Ni germanosilicide on sheet resistance and current drivability of both strained-Si and Si-control nMOSFETs were studied and compared
Cyclical wet clean in DI-O3/SC1/DHF and low temperature bake in HCl/H2 are presented as effective surface treatments for selective SiGe epitaxial deposition used to fabricate embedded SiGe pMOSFETs. The presented methods are most effective for device structures under limited chemical and thermal budgets
In this paper the selective epitaxy of B- and P-doped SiGe layers on either HCl-etched or un-processed Si surfaces for S/D application in CMOS structures have been investigated. The study has focused on how to obtain high quality layers and tackle subjects e.g. dopant incorporation and defect generation in these layers
We have demonstrated the growth of strain-relaxed Ge1-xSnx buffer layers using virtual Ge(001) substrates. PDA effectively promoted the relaxation of the Ge1-x Snx layer, concomitantly with the lateral propagation of preexisting threading dislocations leaving misfit segments at the Ge 1-xSnx/Ge interface. Present results open up a scheme of fabricating strained channels which realize much high performance...
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