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The world of electronic industry, is working with nano-seconds domain of timings, so it's always a challenge for the electronic designers to know the exact, if not exact, then at least 99% accurate of on-silicon-delay values of their design components. By component, means, the smallest possible element for circuit designing. These components are a part of standard library, known as standard cell library...
In the presented paper the improvement of the layout of complex standard gates from the industrial cell library aimed at decreasing the probability of occurrence of undetectable faults is considered. Such improvement allows us to determine the defect coverage table correctly and as a result to estimate properly the optimal sequence of input test pattern for defects detection. The ability of gate layout...
An optical receiver in 0.6 mum BiCMOS technology with voltage-controlled resistor-based variable transimpedance is presented. The frequency bandwidth is independent of the photodiode capacitance. A linearity error smaller than 2.8 %, a sensitivity dynamic range of 76.3 (37.7 dB), an offset voltage smaller than 0.47 mV, a bandwidth up to 204 MHz, and a maximum power consumption of less than 4.05 mW...
In this paper we present a high-frequency extension of our surface-potential-based substrate model for predicting substrate noise coupling in integrated circuits. The model handles an arbitrary number of aggressor and victim devices on a multi-layered substrate with either biased or floating backside. We show that the dielectric properties of the substrate are easily included in this model for providing...
Here we give a new approach for calculating triggering drain bias at the onset of the kink effect utilizing electron drift properties in the channel. This approach directly relates electron mobility in the channel of the PD SOI NMOS devices to the kink effect and gives possibility for determining mobility from the kink voltage Vkink . We compare our theory to the previously published experimental...
Transport and noise characteristic of forward biased 2.3 mum CW GaSb laser diodes were measured in order to evaluate new technology. From the measurement results it follows that noise spectral density related to defects is of 1/f type and its magnitude was found to be proportional to the square of DC forward current at low injection levels
The author first briefly reviews recent success of MOS gate power devices. The main objective is to predict, for the first time, the silicon limit characteristics of IGBTs for its on-resistance and SOA. The author also proposes ideal gate drive in order to realize the ultimate limit of high speed switching of MOS gate power devices. The results lead to new FOM, characterizing the high speed switching...
The inductive switching performance of a smart super-junction (SJ) LDMOS switch is simulated and analysed, together with the reverse recovery properties of its internal diode. The SJ power switch under investigation differs from the conventional one in the so-called SJ structure which, in this case, consists of an array of p-type round pillars embedded in the n-type drift region. In view of the tolerances...
Spontaneous recovery of threshold voltage and channel carrier mobility in DC gate bias stressed power VDMOSFETs, as well as the underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. A chain of mechanisms related to a presence of hydrogen species is proposed to explain the observed changes of oxide-trapped charge...
In this paper the results from a study of multiple high-voltage pulse stressing effects on resistance and low-frequency noise of thick-film resistors based on resistor composition with sheet resistance of 10kOmega/sq are presented. For the experimental purposes a series of thick-film test resistors with identical geometries were realized and exhibited to two types of tests: multiple series of 10 pulses...
Probability density function for the pull-in voltage of the electrostatically actuated micro-bridges due to variations of some dimensional parameters was estimated using Monte Carlo approach. Variations of the pull-in voltage were analyzed in order to find out optimum design parameters taking into account the given process variations in manufacturing micro-bridge structures
In this paper, we elaborate the nonlinear model based on ferroelectric properties of microtubules (MTs) and triggered by hydrolysis of GTP (guanosine triphosphate) followed by conversion of chemical energy into large conformational rotation of corresponding tubulin dimer. We attempted to elucidate some functional properties of microtubules pertaining kinesin motor protein on the basis of this elegant...
This paper describes the design and implementation of an innovative high-speed data buffer system for optical interconnects based on electrically reprogrammable FPGAs. It is characterized by high transfer rates and the dense integration of electrical and optical components on the basis of a printed circuit board (PCB). The high data rates and the highly parallelized system operation require a specific...
The challenges in clocking high speed interfaces such as the communication between multi micro-processor systems or the communication between micro-processor and off-chip memory was introduced by our need for high data rate with low bit-error-rates (BER). Minimization of clock jitter is one of the main challenges in making the high data rate links work. There are a series of issues affecting clock...
Analog to digital converter (ADC) is the crucial part of many mixed-signal ICs because it interfaces analog signals from real world with digital logic on a chip. Faults made during ADC hardly can be repaired within the digital part. Therefore, functional testing of ADC is a very important task especially during prototyping. In this paper one laboratory ADC tester is proposed. It is based on NI-6251...
In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer (Fenghao and Svensson, 2000). In this paper, we propose a pulsewidth control loop referred as APWCL (adaptive pulsewidth control loop) that adopts the same architecture as the conventional PWCL, but with two modifications. The first one relates to implementation...
This article describes a measurement environment for study of two CMOS defect types: opens and shorts. These defect types are physically implemented in silicon in a big variety of locations inside a set of digital standard cells and small circuits. The integrated circuit (IC) with the collection of defects is mounted onto a plug-and-play measurement box, which is connected to the PC via USB cable...
This paper discusses on the effect of number of zincation in electroless nickel immersion gold (ENIG) under bump metallurgy (UBM) on reliability in microelectronics packaging. Double and triple zincation of ENIG methods were used as comparison study. The effect of number of zincation to surface roughness and surface morphology were investigated. All samples were subjected to reliability tests such...
In this study, we designed and simulated MOS devices having alternative gate dielectrics and examined their electrical behaviour as well as their effectiveness on the performance of a DRAM cell containing them. The devices under test had gate dielectrics of SrTiO3, (Ba1-xSrx)TiO3, TiO2, Ta2O5, Y2O3 and (Pb1 Lax)TiO3. Equivalent oxide thicknesses were derived between 0.95 and 4 nm. Among the candidate...
The temperature dependence of resistivity, structure and thermal expansion of composites based on polymer blend polypropylene/co-polyamide (PP/CPA) filled with dispersed iron (Fe) has been studied. The dependence of conductivity on filler content shows percolation behavior with the values of the percolation thresholds equal to 5 vol.% for the filled blend PP/CPA-Fe with two steps character of the...
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