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This paper presents the TinyCAN, a resource constrained controller area network controller implemented in VHDL language. The core description is fully synthesizable and fits in a FPGA-based platform occupying a maximum of 366 look-up tables. An enhanced error control strategy was elaborated with the aim of producing a more suitable behavior for safety-critical applications. For all that, compatibility...
In this paper we propose a new reconfigurable architecture for sensor nodes, called RANS-300, which can operate in applications demanding low power to high performance, although sacrificing the lifetime of the sensor node. This node has a FPGA board, which can be dynamically reconfigured to add new configuration, and has a Compact Flash device to expand the node possibilities
This paper describes the hardware/software co-design of a multithreaded RTOS kernel on a new Xilinx Virtex II Pro FPGA. Our multithreaded RTOS kernel is an integral part of our hybrid thread programming model being developed for hybrid systems which are comprised of both software resident and hardware resident concurrently executing threads. Additionally, we provide new interrupt semantics by migrating...
The use of hybrid technologies creates the opportunity to combine nano-scale technologies, microelectronics and neuroscience in order to build devices for non-invasive stimulation and recording of cultured neural cells at nano-level. A hybrid neuro-electronic platform for neuroprocessing is proposed as a means to develop a new intelligent information system biologically inspired. The platform is designed...
This paper describes an improved approach to design a Takagi-Sugeno zero-order type fast parameterized digital fuzzy logic controller (DFLC) processing only the active rules (rules that give a non-null contribution for a given input data set), at high frequency of operation, without significant increase in hardware complexity. To achieve this goal, an improved method of designing the fuzzy controller...
The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based...
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