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Increasing use of scratch-pad memories (SPMs) in embedded systems makes it imperative to consider optimizations tailored to their needs. Since these memories are managed by software, they present unique opportunities to the designer/compiler writer as far as energy optimizations are concerned. This paper proposes and quantifies the benefits of a compiler-directed energy optimization scheme for banked...
Our goal in this paper is to demonstrate that an optimizing compiler can be very successful in reducing leakage energy consumption of on-chip SMMs for array-dominated embedded applications
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design methodology for a logic-in-memory architecture where each of memory modules is connected to its dedicated processing element (PE). An efficient memory allocation to minimize the number of memory modules and PEs under a time constraint...
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