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Mask programmable gate arrays (MPGAs) are an attractive solution to reduce design cost and turnaround time in ultra-deep submicron technologies. Several design methodologies have been proposed in the recent years for converting an evaluated field-programmable gate-array (FPGA) prototype design into an MPGA. In this paper, we investigate a predefined regular routing architecture of an MPGA. The routing...
Hash functions play an important role in modern cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby...
Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level adequation algorithm architecture process. We present a method generates automatically the design for both partially and fixed parts of FPGAs
The effect of components' region-constrained placement on reducing internal nets total capacitance and the corresponding change in internal nets' total dynamic power consumption is investigated. Two logic circuits were specified as components covering around 80% of total FPGA busy gates. These components are multiplexers and adders along with multipliers. Each of these components was implemented on...
Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while design-time, e.g. for system-on-chip (SoC) component design, is not sufficient if the possibility of run-time reconfiguration of novel architectures...
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfiguration to adapt FPGA operation to changing application requirements has been hampered by slow reconfiguration times, and poor CAD tool support. In this paper, a new architecture, QUKU (pronounced cuckoo), is described which...
Impact of variations in different process parameters like, gate length, threshold voltage, oxide thickness etc. have been discussed in different components of digital circuits extensively in recent times. The various manufacturing effects on different process parameters have been demonstrated in (Borkar et al., 2004) and (Nassif, 2001). Degradation in the operating frequencies by nearly 2times and...
Our recent work in embedded FPGAs has been focused on a soft IP approach where programmable fabrics are described at the RTL level and implemented using the ASIC digital flow and generic standard cells. Early results showed significant penalties in area, delay, and power overhead. However, using tactical standard cells and a structured physical design approach within such a flow, we were able to obtain...
In this paper, we present a communication protocol for network on chip architectures which have complex packet switched communication protocols. In order to manage this complexity and advance reusability, a layered approach is taken. It is a 4-layered protocol stack including application, transaction, data-link and physical layers. Our protocol stack supports the best effort traffic as well as guaranteed...
This paper describes a real time reconfigurable (RTR) micro-FPGA using new non volatile memory. Magnetic tunneling junctions (MTJ) used in magnetic random access memories (MRAM) are compatible with classical CMOS processes. Moreover remanent property of such a memory could limit configuration time and power consumption required at each power up of the device. Each configuration memory point has to...
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