The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Tasks such as module selection, scheduling and allocation involved in the architecture synthesis problem of VLSI chips are tightly interdependent. Simultaneous optimization of these tasks is necessary for the global solution of a design. The authors present a new graph model for the integrated architecture synthesis problem of VLSI chips and then formulate the problem as a partial clique partition...
The authors present a new systematic approach toward global hardware synthesis of DSP ASICs from behavioral specifications. A VHDL behavioral description is the input language of the COMET system. Given the stage time, data initialization interval (DII), and area-time tradeoff weight, a VHDL structural description is generated. A set of global data flow graph transformations is performed to minimize...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.