Power dissipation minimization during programming the RRAM array is the key constraint for the choice of the selector. Recently impact ionization based steep-sub-threshold device has been proposed by TCAD simulations. Si NPN based biristor shows steep sub-threshold slope at high bias. We have experimentally demonstrated sub-0.5V impact ionization in Si based NIPIN device. This paper identifies transient non-linearity, which reduces the IOFF by at least 2 orders compared to steady state IOFF. A program scheme is presented to show 1.5 orders improvement in total power consumed.