An 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing with an area-efficient 8b offset calibration DAC. A prototype in 28nm CMOS achieves 6.8 ENOB and 50fJ/c-s at DC and 6.3 ENOB and 68fJ/c-s at Nyquist, at a sample rate of 1.3GS/s. The measured SNDR/SFDR improve from 29.2/40.7dB to 42.6/57.7dB after calibration. The active area is 0.05mm2.
