A Viterbi algorithm for decoding of the convolutional code is a powerful method for controlling errors in data transmission over a noisy channel. It is based on maximum likelihood algorithm for decoding the data. However, the hardware implementation of Viterbi algorithm become crucial as it consumes large resources due to its complexity. This paper discussed the implementation of ½ rate convolutional encoder and hard decision Viterbi decoder in VHDL using Model Sim and Xilinx ISE tools for simulation and synthesis of modules respectively. BER plots and simulated output waveforms are also presented.