Design of memory I/O channels or general purpose I/O (GPIO) has become very complicated as we aim for higher speeds, higher I/O count and cost-effective solutions. At these speeds, package and die discontinuities cause more deterministic jitter and noise due to inter-symbol interference (ISI) effects and crosstalk. Therefore, to improve timing margins, engineers have to carefully study impact of package and die capacitive/inductive discontinuities in order to improve the portion contributing to eye diagram closure. This paper specifically shows how these discontinuities affect DDR4 memory system simulations differently based on the direction of communication, that is, Write (die to DRAM) and Read (DRAM to die) and then offers practical solutions that can be used to mitigate jitter and improve margins.