A new design of half pre-charged CMOS dynamic logic circuit is proposed in this paper. By adding a transmission transistor and a pre-charge transistor along with an optimization of the comparator structure, the DC short circuits during pre-charge and evaluation phases are both eliminated, which in turn reduced the overall power consumption significantly. Simulation results show that for a two input AND gate dynamic logic, the proposed circuit can lower power consumption by 90% compared to the reference design.