Novel 300-V Field-MOS FETs were developed for high-voltage analog switch circuits. The breakdown voltages of the Field-NMOS/PMOS FETs were 410 V/370 V with the specific on-resistance of 1850/11 000 . The vertical and lateral electric fields were both optimized to maximize the breakdown voltage over a wide range of substrate voltages; the device layout optimization included adjusting the silicon-on-insulator thickness and the use of a deep well and a field plate. A low specific on-resistance was obtained as a result of using an extended-drain layer, in addition to the potential linearity of the current pathway in the drift region. This technology can be applied to 300-V analog switch ICs that need to have a low leakage current and a low switching resistance.