Gate leakage is one of the important parameter expected to limit the performance of Tunnel FETs. We have simulated the effect of gate dielectric thickness on gate leakage in Tunnel FETs, using two dimensional numerical simulations. It has been observed that gate leakage considerably affects the subthreshold characteristics of TFETs. It was found to be most important component of off-state current and should be considered in future TFET device design. Effects of gate metal workfunction on device characteristics, particularly, gate leakage and origin of reverse tunneling at drain have also been discussed.