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Source

2009 IEEE Asian Solid-State Circuits Conference > 73 - 76

Abstract

Identifiers

book ISBN : 978-1-4244-4433-5
book e-ISBN : 978-1-4244-4434-2
DOI 10.1109/ASSCC.2009.5357182

Authors

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Wei-Hao Chiu

  • Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Tai-Shun Chang

  • Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Tsung-Hsien Lin

  • Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Keywords

phase noise charge pump circuits CMOS integrated circuits delta-sigma modulation phase locked loops size 0.18 μm CMOS delta-sigma fractional-N phase-locked loop CP circuit reference cycle up-down current difference in-band phase noise fractional spurs TSMC CMOS process frequency 2.4 GHz voltage 1.8 V power 23 mW charge pump current missmatch calibration ΣΔ fractional-N PLL Calibration Charge pumps Voltage-controlled oscillators Modulation Current measurement

phase noise charge pump circuits CMOS integrated circuits delta-sigma modulation phase locked loops size 0.18 μm CMOS delta-sigma fractional-N phase-locked loop CP circuit reference cycle up-down current difference in-band phase noise fractional spurs TSMC CMOS process frequency 2.4 GHz voltage 1.8 V power 23 mW charge pump current missmatch calibration ΣΔ fractional-N PLL Calibration Charge pumps Voltage-controlled oscillators Modulation Current measurement

Additional information

Data set: ieee

Publisher

IEEE
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