<para> The feasibility of using sub-50-nm dual-gate thin-film transistors (TFTs) for monolithic 3-D integrated Flash memories is shown. Silicon-based TFTs with the smallest length and width demonstrated to date have been assembled into series strings of up to 64 cells. Read- and program-pass disturbs, the bane of any <emphasis emphasistype="smcaps">nand</emphasis> charge-trap Flash approach, have been extinguished. The ability to independently optimize the ONO structure from pass disturbs results in excellent endurance and retention after cycling. Monolithic 3-D integration is ensured through close-to-zero source/drain diffusion at temperatures required for layer stacking. Further scalability is assured through the excellent electrostatic control that results from the cell's elemental structure. Finally, the combination of “CMOS-friendly” materials and tried-and-trusted low-power program and erase mechanisms makes this approach a powerful technology contender for post- <emphasis emphasistype="smcaps">nand</emphasis> 3-D Flash. From all nonfloating-gate monolithic 3-D approaches being touted, this is the first where a sub-50-nm device has been shown to withstand the temperature budget of subsequent layers. </para>