Quiescent supply current (IDDQ) is a very effective test method for CMOS circuits. However, IDDQ vector verification and debugging may take considerable time and effort; various problems have been encountered in this process, so different tools and methodologies have been devised to address them. For pre-silicon IDDQ vector verification, a modular approach is adopted. IDDQ is estimated for each vector based on leakage libraries of cells, and cell constraints can be verified automatically. For post-silicon IDDQ vector issues, methods and analysis tools have been developed to identify the root causes. Scan cell and net value analysis will identify critical scan cells and nets, which will determine whether an IDDQ pattern passes or fails, thus revealing the source of the extra leakage. These methodologies are proven to be very successful for IDDQ vector debug and IDDQ diagnosis.