The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The voltage-time domain (VT) characteristics of the CMOS NOR logic circuit are investigated using a switch matrix technique (SMT). VT performance is analyzed following gate oxide wearout in a pMOSFET, induced by applying a constant voltage stress (CVS) at -4.0 V. Results for the NOR VT characteristics show approximately 30% increase in rise time a considerable digression from nominal operation