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Field Programmable Gate Array (FPGA) system is widely used in deep learning application and cloud system for acceleration. Quality and reliability of IP block is essential to the successful development of today's complex hardware acceleration design. In this paper, we discuss the important issues of quality and reliability of digital soft IP, and propose a qualification measurement system that can...
In this paper, to solve the problem that there are shortage of united frameworks or the frameworks do not match very well with the process for NBFs in sequence cryptograms, we analyzed the processing of sequence cryptograms, describe the abstract model and devise a reconfigurable framework for the existing NBFs. In particular, in order to get excellent area utilization, we firstly study on the proposed...
At present there is a big demand to the stability test instrument. In this article ,an instrument for measuring Allen devision is designed based on the DDS technology as well as a high precious frequency measurement method that measure the difference frequency's period of the under test frequency and the reference. The instrument's background stability surpasses 4.0×10−12/1s, 1.5×10−12/10s and its...
A deinterleaving algorithm of radar signal based on DSP is presented in this paper, which is according to the structure of the deinterleaving system, characteristics of PDW (pulse descriptor word) and histogram method. The threshold determination, accumulation of PRI (pulse repetition interval) and others in the algorithm applied in different fields are introduced in detail. The experimental results...
A low power and dynamic reconfigurable hardware architecture of E0 algorithm is presented, which can satisfy sixteen different LFSRs in the Bluetooth telecommunication systems. The new LFSR design techniques can be also useful in any reconfigurable LFSR. To reduce the conventional switching activity, we proposed the clock-gatiing technique to implement the LFSR. As to the different low power method,...
A high-speed and dynamic reconfigurable hardware architecture of A5 algorithm is presented, which can satisfy the different characteristic of A5/1 and A5/2 algorithm. To save the hardware cost and get shorter critical path, we proposed reconfigurable clock controlling unit and output function, which can be reconfigured to realize the critical function of two algorithms. As to the different high-speed...
A high-speed and dynamic reconfigurable hardware architecture of grain algorithm is presented, which can satisfy the different characteristic of Grain-80 and Grain-128 algorithm. To save the hardware cost and get shorter critical path, we proposed tree network to implement linear and nonlinear feedback function. As to the different high-speed method, this paper perform detailed comparison and analysis...
Harmonic signal generator whose frequency, phase and harmonic proportion are adjustable is designed for the detecting equipment of power system. The principle of DDS and the design requirement are introduced. Then the algorithm of ROM compression based on the symmetry of sine wave is expounded. Finally using Altera FPGA, the detail design of the whole system is presented and test waveforms are given...
This paper presents a signal generator for imaging radar and other area. The system has two analog signal channels which use high-speed, high-precision DAC converters. The data transport bus employs FPDP (front panel data port) interface. FPGA (field programmable gate array) realized the control of the entire module including FPDP interface, DAC control and data format transform. The signal conversion...
A fast algorithm of complementary code keying (CCK) applied in DSP for wireless local area networks (WLANs) is presented in the paper. It simplifies the decoding process by modifying the fast walsh transform (FWT) architecture, which is based on the analysis of feature of FWT and CCK in the IEEE 802.11b standard. Besides, all the complex multiplications are replaced by complex additions. Especially...
A new design method for the real-time image processing system based on field programmable gate array (FPGA) and digital signal processing (DSP) structure is presented in the paper. In the practical system, FPGA is used to be logic unit for sensor interface protocol and complete image preprocessing and display of PAL video; DSP is applied as the main processing unit which is extendable for better performance;...
Nowadays, with the growing of multimedia applications, requirement for embedded multimedia system becomes popular. The implementation of a multi-model video encoder is introduced, which is composed of DSP (digital signal processor) and FPGA (field programmable gate array). The FPGA complete some auxiliary tasks, such as video acquisition and YUV separation, while the DSP is dedicated for video compression...
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