The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents the complete link budget analysis of a VLC system. By calculating the transmitter's emitted power, the channel path loss and the receiver's input referred noise, the system SNR and BER performance are derived. Furthermore, a VLC transceiver system is implemented with the analog front-end using discrete components while the baseband in FPGA, and the experimental results demonstrate...
This paper introduces a digital pulse generation scheme for ultra-wideband (UWB) system, based on which bipolar modulation is realized. Simulation and experiment results are given, which show that the proposed scheme is capable of 100Mbps data transmission.
A customized reconfigurable interconnection network (CRIN) refers to a minimal switching network, yielding routing solutions for any element in a pre-given set of routing requirements. The CRIN design problem looks for the best performance and resource-flexibility trade-off between two extreme design contexts ASIC and FPGA. In this paper we give the modeling of this problem for both directed and undirected...
An infrared real-time imaging system has been developed for the uncooled infrared focal plane array (UIRFPA). By using this system, infrared video signal from UIRFPA is corrected and displayed. Taking advantage of the high speed and parallel computation of FPGA, it is used as the core part of the system to complete the functions such as sampling, data caching, nonlinear correction and image enhancement...
This work presents a novel, accurate, and fast post-layout logic perturbation method for improving LUT-based FPGA routing without affecting the placement. The ATPG-based rewiring techniques are used to design the rewiring engine, which is embedded into VPR, the most powerful academic FPGA CAD tool currently. Compared with VPR's high-quality results, our method can reduce critical path delay by up...
One unique property of an FPGA chip is that any logic perturbation inside its Look-Up-Tables (LUTs) is totally area/delay-free. Amongst others, this free LUT-internal resource perturbation can also be used to trade for critical LUT-external logic/wire removals for EDA improvements, an extra flexibility ignored before. Using rewiring technique for such logic perturbations, we show that significant...
With the rapid progress of VLSI technology FPGAs' performance efficiency has become the main concern of designers and manufacturers. Our goal in this work is to propose a new FPGA structure to reduce critical net delay without increasing routing area. The augmented connection box is proposed. It allows two different signals to share one track in a connection box by inserting additional switches where...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.