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In this study, we have investigated the multi-level cell (MLC) characteristics and variability analysis of multiple resistance states of one of the most promising and extensively studied binary oxide (HfOx) based nanometer scale RRAM stack by varying the switching current. The device size and thickness of stack layers were confirmed by transmission electron microscope (TEM) images. In the CMOS friendly...
We report a novel contact technology comprising Selenium (Se) co-implantation and segregation to reduce Schottky barrier height PhiBn and contact resistance for n-FETs. Introducing Se at the silicide-semiconductor interface pins the Fermi level near the conduction band, and achieves a record low PhiBn of 0.1 eV on Si:C S/D stressors. Comparable sheet resistance and junction leakage are observed with...
We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction...
We report the integration of nickel platinum germanosilicide (Ni1-yPtySiGe) contacts in tri-gate FinFETs with silicon germanium source/drain stressors for enhanced drive current performance. The structural and electrical properties of Ni1-yPtySiGe contacts with platinum (Pt) concentrations up to 20 atomic % (at. %) were explored for FinFET integration. Our results show that Ni1-yPtySiGe incorporated...
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